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307 lines
19 KiB
307 lines
19 KiB
3 years ago
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;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* DSPLIB DSP Signal Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.7 Sun Sep 29 03:32:22 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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* ========================================================================= *
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* TEXAS INSTRUMENTS, INC. *
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* *
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* NAME *
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* DSP_fir_r4: FIR Filter (radix 4) *
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* *
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* *
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* REVISION DATE *
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* 10-Aug-2001 *
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* *
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* USAGE *
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* This routine is C-callable and can be called as: *
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* *
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* void DSP_fir_r4 *
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* ( *
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* const short *restrict x, /* Input array [nr+nh-1 elements] */ *
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* const short *restrict h, /* Coeff array [nh elements] */ *
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* short *restrict r, /* Output array [nr elements] */ *
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* int nh, /* Number of coefficients. */ *
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* int nr /* Number of output samples. */ *
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* ) *
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* *
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* ARGUMENTS PASSED *
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* *x -> A4 *
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* *h -> B4 *
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* *r -> A6 *
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* nh -> B6 *
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* nr -> A8 *
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* *
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* DESCRIPTION *
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* Computes a real FIR filter (direct-form) using coefficients *
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* stored in vector h. The real data input is stored in vector x. *
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* The filter output result is stored in vector r. Input data and *
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* filter taps are 16-bit, with intermediate values kept at 32-bit *
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* precision. Filter taps are expected in Q15 format. *
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* *
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* The following is a natural C implementation with no restrictions. *
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* This version has restrictions as noted in the ASSUMPTIONS below. *
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* *
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* void DSP_fir_r4 *
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* ( *
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* const short *restrict x, *
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* const short *restrict h, *
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* short *restrict r, *
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* int nh, *
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* int nr *
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* ) *
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* { *
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* int i, j, sum; *
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* *
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* for (j = 0; j < nr; j++) *
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* { *
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* sum = 0; *
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* for (i = 0; i < nh; i++) *
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* sum += x[i + j] * h[i]; *
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* r[j] = sum >> 15; *
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* } *
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* } *
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* *
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* ASSUMPTIONS *
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* Number of taps: 'nh' >= 8, multiple of 4 *
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* Number of samples: 'nr' >= 4, multiple of 4 *
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* *
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* NOTES *
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* This function blocks interrupts for its entire duration. It is *
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* interrupt tolerant, but not interruptible. *
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* *
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* MEMORY NOTE *
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* No memory bank hits under any conditions. *
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* This code is a LITTLE ENDIAN implementation *
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* *
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* TECHNIQUES *
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* 1. Load double word instruction is used to simultaneously *
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* load four values in a single clock cycle. *
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* 2. The inner loop is unrolled four times *
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* *
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* CYCLES *
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* (8 + nh) * nr/4 + 9 *
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* *
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* For nh = 12 and nr = 12, cycles = 69 *
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* *
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* CODESIZE *
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* 308 bytes. *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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.sect ".data:copyright_h"
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; ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== ;
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.asg A0, A_s ; flag for sum0a,1a,2a,3a: = 1
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.asg A1, A_i ; inner loop count = 2
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.asg A2, A_rj ; outer loop cont j_cnt = (nr+3)>>2
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.asg A4, A_x_ptr ; input array pointer
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.asg A6, A_r_ptr ; output array pointer
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.asg A7, A_nh_x ; = (nh+3)>>2+1
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.asg A8, A_nr ; = (nr+3)
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.asg A16, A_h10 ; coef: h[1:0]
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.asg A17, A_h32 ; coef: h[3:2]
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.asg A18, A_x10 ; input: x[1:0]
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.asg A19, A_x32 ; input: x[3:2]
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.asg A20, A_x21 ; input: x[2:1]
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.asg A21, A_prod00_11; = x[0]*h[0] + x[1]*h[1]
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.asg A22, A_prod22_33; = x[2]*h[2] + x[3]*h[3]
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.asg A23, A_prod32_43; = x[3]*h[2] + x[4]*h[3]
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.asg A24, A_prod10_21; = x[1]*h[0] + x[2]*h[1]
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.asg A26, A_sum0a ; = sum0b + x[2]*h[2] + x[3]*h[3]
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.asg A26, A_sum0b ; = sum0a + x[0]*h[0] + x[1]*h[1]
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.asg A27, A_sum1a ; = sum1b + x[1]*h[0] + x[2]*h[1]
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.asg A27, A_sum1b ; = sum1a + x[3]*h[2] + x[4]*h[3]
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.asg A25, A_sum0 ; = sum0a >>15 for r[0]
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.asg A28, A_sum1 ; = sum1a >>15 for r[1]
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.asg B0, B_j ; outer loop flag; if 0,branch to iloop
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.asg B4, B_h_ptr ; coef array pointer
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.asg B5, B_iloop ; iloop label address
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.asg B6, B_nh ; initial value for B_j, if A_rj != 0
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.asg B7, B_nh_h ; addr offset for h_ptr: = (nh+3)>>2+1
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.asg B8, B_h_ptr1 ; temp coef array ptr: point to h[nh]
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.asg B8, B_r10 ; output: r[1:0]
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.asg B9, B_r32 ; output: r[3:2]
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.asg B9, B_x32 ; input: x[3:2]
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.asg B16, B_h10 ; coef: h[1:0]
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.asg B17, B_h32 ; coef: h[3:2]
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.asg B18, B_x54 ; input: x[5:4]
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.asg B19, B_x76 ; input: x[7:6]
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.asg B20, B_x43 ; input: x[4:3]
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.asg B21, B_x65 ; input: x[6:5]
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.asg B22, B_prod42_53; = x[4]*h[2] + x[5]*h[3]
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.asg B23, B_prod20_31; = x[2]*h[0] + x[3]*h[1]
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.asg B24, B_prod30_41; = x[3]*h[0] + x[4]*h[1]
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.asg B25, B_prod52_63; = x[5]*h[2] + x[6]*h[3]
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.asg B26, B_sum2a ; = sum2b + x[2]*h[0] + x[3]*h[1]
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.asg B26, B_sum2b ; = sum2a + x[4]*h[2] + x[5]*h[3]
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.asg B27, B_sum3a ; = sum3b + x[3]*h[0] + x[4]*h[1]
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.asg B27, B_sum3b ; = sum3a + x[5]*h[2] + x[6]*h[3]
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.asg B28, B_sum0 ; = A_sum0
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.asg B29, B_sum1 ; = A_sum1
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.asg B30, B_sum2 ; = sum2a >>15 for r[2]
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.asg B31, B_sum3 ; = sum3a >>15 for r[3]
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.sect ".text:_fir_r4"
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.global _DSP_fir_r4
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_DSP_fir_r4:
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; ======================= SETUP / LOOP PIPE-UP CODE ======================= ;
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LDNDW .D1T2 *++A_x_ptr,B_x76:B_x54 ; load B_x76:x54
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|| ADD .L1 3,A_nr,A_nr ; nr + 3
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|| SHR .S2 B_nh,2,B_nh ; i_cnt = nh>>2
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|| B .S1 dint0 ; protect setup code
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LDNDW .D1T1 *-A_x_ptr[1],A_x32:A_x10 ; load A_x32:x10
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|| SHR .S1 A_nr,2,A_rj ; j_cnt = (nr+3)>>2
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LDNDW .D2T1 *B_h_ptr,A_h32:A_h10 ; load A_h32:h10
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|| SUB .L1 A_rj,1,A_rj ; j_cnt -= 1
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LDNDW .D2T2 *B_h_ptr++,B_h32:B_h10 ; load B_h32:h10
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||[A_rj]MV .S2 B_nh,B_j ; jloop cnt
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|| MV .S1X B_nh,A_i ; i_cnt = nh>>2
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|| SUB .L2 -2,B_nh,B_nh_h ; addr offset for h_ptr
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LDNDW .D1T2 *++A_x_ptr,B_x76:B_x54 ; load B_x1110:x98
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|| MVK .S1 1,A_s ; sync for sum0a,1a,2a,3a
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|| ADDKPC .S2 iloop,B_iloop,0 ; store iloop addr to reg
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|| SUB .L1X -1,B_nh,A_nh_x ; addr offset for x_ptr
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LDNDW .D1T1 *-A_x_ptr[1],A_x32:A_x10 ; load A_x76:x54
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|| B .S1 iloop ;
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|| ZERO .L2 B_sum3a:B_sum2a
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dint0: LDNDW .D2T1 *B_h_ptr,A_h32:A_h10 ; load A_h76:h54
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|| PACKLH2 .S2X B_x54,A_x32,B_x43 ; @ input: x[4:3]
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|| ZERO .L1 A_sum1a:A_sum0a
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||[!A_rj]ADD .L2 5,B_nh,B_j ; if last jloop, will not
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; ========================== "ILOOP" LOOP KERNEL ========================== ;
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iloop:
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DOTP2 .M1 A_x10,A_h10,A_prod00_11 ; @ x[0]*h[0] + x[1]*h[1]
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||[!A_s]ADD .S1 A_sum0a,A_prod00_11,A_sum0b ; x[0]*h[0] + x[1]*h[1]
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|| DOTP2 .M2X B_x54,A_h32,B_prod42_53 ; @ x[4]*h[2] + x[5]*h[3]
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||[!A_s]ADD .L2 B_sum2a,B_prod42_53,B_sum2b ; x[4]*h[2] + x[5]*h[3]
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|| PACKLH2 .S2 B_x76,B_x54,B_x65 ; @ input: x[6:5]
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|| LDNDW .D2T2 *B_h_ptr++,B_h32:B_h10 ; load coef: h32:h10
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|| PACKLH2 .L1 A_x32,A_x10,A_x21 ; input: x[2:1]
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||[!B_j]ADDAD .D1 A_x_ptr,A_nh_x,A_x_ptr ; reset the input pointer
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DOTP2 .M1 A_x32,A_h32,A_prod22_33 ; x[2]*h[2] + x[3]*h[3]
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||[!A_s]ADD .L1 A_sum0b,A_prod22_33,A_sum0a ; x[2]*h[2] + x[3]*h[3]
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|| DOTP2 .M2 B_x65,B_h32,B_prod52_63 ; x[5]*h[2] + x[6]*h[3]
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||[!A_s]ADD .S2 B_sum3a,B_prod52_63,B_sum3b ; x[5]*h[2] + x[6]*h[3]
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|| LDNDW .D1T2 *++A_x_ptr,B_x76:B_x54 ; load intput: x76:x54
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||[!B_j]ADDAD .D2 B_h_ptr,B_nh_h,B_h_ptr ; reset the coef pointer
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||[ A_i]SUB .S1 A_i,1,A_i ; @
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|| MV .L2X A_x32,B_x32 ;
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DOTP2 .M2 B_x32,B_h10,B_prod20_31 ; x[2]*h[0] + x[3]*h[1]
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||[!A_s]ADD .L2 B_sum2b,B_prod20_31, B_sum2a; x[2]*h[0] + x[3]*h[1]
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|| DOTP2 .M1X B_x43,A_h32,A_prod32_43 ; x[3]*h[2] + x[4]*h[3]
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||[!A_s]ADD .L1 A_sum1a,A_prod32_43,A_sum1b ; x[3]*h[2] + x[4]*h[3]
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||[ A_i]B .S1 iloop ; inner loop brach
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||[!B_j]B .S2 B_iloop ; outer loop brach
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|| LDNDW .D1T1 *-A_x_ptr[1],A_x32:A_x10 ; load input: x[32]:x[10]
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|| SUB .D2 B_j,1,B_j ; count for outer loop
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DOTP2 .M1X A_x21,B_h10,A_prod10_21 ; x[1]*h[0] + x[2]*h[1]
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||[!A_s]ADD .D1 A_sum1b,A_prod10_21,A_sum1a ; x[1]*h[0] + x[2]*h[1]
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|| DOTP2 .M2 B_x43,B_h10,B_prod30_41 ; x[3]*h[0] + x[4]*h[1]
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||[!A_s]ADD .L2 B_sum3b,B_prod30_41,B_sum3a ; x[3]*h[0] + x[4]*h[1]
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|| LDNDW .D2T1 *B_h_ptr,A_h32:A_h10 ; load coef: h32:h10
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||[ A_s]ZERO .L1 A_s ; @flag for sum0a,1a,2a,3a
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|| PACKLH2 .S2X B_x54,A_x32,B_x43 ; @ input: x[4:3]
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; ========================= END OF "ILOOP" KERNEL ========================= ;
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SHR .S1 A_sum0a,15,A_sum0 ; = sum0a >>15 for r[0]
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|| ADD .L2 B_sum2a,B_sum2a,B_sum2 ; = sum2a <<1 for r[2]
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||[A_rj]LDNDW .D2T2 *B_h_ptr++,B_h32:B_h10 ; p load intput: x[3:2]:x[1:0]
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||[!A_rj]RET .S2 B3
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||
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||
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[A_rj]LDNDW .D1T2 *++A_x_ptr,B_x76:B_x54 ; p load intput: x[7:6]:x[5:4]
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||
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|| SHR .S2X A_sum1a,15,B_sum1 ; = sum1a >>15 for r[1]
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||
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|| ADD .D2 B_sum3a,B_sum3a,B_sum3 ; = sum3a <<1 for r[3]
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||
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|| MV .S1X B_nh,A_i ; initialize inner loop count
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||
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|| ZERO .L2 B_sum3a:B_sum2a ; p initialize B_sum3a,2a
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||
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||
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PACK2 .L2X B_sum1,A_sum0,B_r10 ; r[1:0]
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||
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|| PACKH2 .S2 B_sum3,B_sum2,B_r32 ; r[3:2]
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||
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||[A_rj]LDNDW .D2T1 *B_h_ptr,A_h32:A_h10 ; p load coef: h[3:2]:h[1:0]
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||
|
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|| MVD .M1X B_x76,A_x32 ; p load intput: x[3:2]
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||
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|| MVK .D1 1,A_s ; p flag for accum sum0a..3a
|
||
|
|
||[A_rj]B .S1 iloop ; p branch to outer loop
|
||
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||[A_rj]SUB .L1 A_rj,1,A_rj ; count down for outer loop
|
||
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|
||
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|
STNDW .D1 B_r32:B_r10,*A_r_ptr++ ; p store output r[3:2]:r[1:0]
|
||
|
|
|| MVD .M1X B_x54,A_x10 ; p load intput: x[1:0]
|
||
|
|
||[A_rj]MV .S2 B_nh,B_j ; initialize outer loop count
|
||
|
|
||[!A_rj]ADD .D2 5,B_nh,B_j ; initialize outer loop count
|
||
|
|
|| ZERO .L1 A_sum1a:A_sum0a ; p initialize B_sum1a,0a
|
||
|
|
|| PACKLH2 .L2X B_x54,A_x32,B_x43 ; @ input: x[4:3]
|
||
|
|
; ============================ END OF "JLOOP" ============================= ;
|
||
|
|
NOP 2
|
||
|
|
; ============================= BRANCH OCCURS ============================= ;
|
||
|
|
|
||
|
|
* ========================================================================= *
|
||
|
|
* End of file: dsp_fir_r4.asm *
|
||
|
|
* ------------------------------------------------------------------------- *
|
||
|
|
* Copyright (c) 2003 Texas Instruments, Incorporated. *
|
||
|
|
* All Rights Reserved. *
|
||
|
|
* ========================================================================= *
|