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259 lines
16 KiB
259 lines
16 KiB
3 years ago
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;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* IMGLIB DSP Image/Video Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.4 Sun Sep 29 03:32:30 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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* ========================================================================= *
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* TEXAS INSTRUMENTS, INC. *
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* *
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* NAME *
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* IMG_thr_le2thr *
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* *
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* *
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* REVISION DATE *
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* 13-Sep-2002 *
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* *
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* USAGE *
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* This routine has the following C prototype: *
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* *
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* void IMG_thr_le2thr *
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* ( *
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* const unsigned char *in_data, /* Input image data */ *
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* unsigned char *restrict out_data, /* Output image data */ *
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* short cols, short rows, /* Image dimensions */ *
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* unsigned char threshold /* Threshold value */ *
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* ) *
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* *
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* This routine performs a thresholding operation on an input *
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* image in in_data[] whose dimensions are given in the arguments *
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* 'cols' and 'rows'. The thresholded pixels are written to the *
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* output image pointed to by out_data[]. The input and output *
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* are exactly the same dimensions. *
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* *
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* DESCRIPTION *
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* Pixels that are above the threshold value are written to the *
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* output unmodified. Pixels that are greater than the threshold *
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* are set to the threshold value in the output image. *
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* *
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* The exact thresholding function performed is described by *
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* the following transfer function diagram: *
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* *
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* *
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* 255_| *
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* | / *
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* | / *
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* O | / *
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* U | / *
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* T th _|_________ / *
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* P | . *
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* U | . *
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* T | . *
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* | . *
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* 0_|_________.__________ *
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* | | | *
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* 0 th 255 *
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* *
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* INPUT *
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* *
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* Please see the IMGLIB functions IMG_thr_gt2thr, IMG_thr_le2min *
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* and IMG_thr_gt2max for other thresholding functions. *
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* *
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* ASSUMPTIONS *
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* The input and output buffers do not alias. *
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* *
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* The input and output buffers must be double-word aligned. *
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* *
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* The total number of pixels rows*cols must be at least *
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* 16 and a multiple of 16. *
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* *
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* TECHNIQUES *
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* The loop is unrolled 16x. Packed-data processing techniques *
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* allow us to process all 16 pixels in parallel. *
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* *
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* Two LDDW instructions load in 16 pixels, designated p0 thru p9 *
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* pA thru pF. These pixels are packed in the four registers pFEDC, *
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* pBA98, p7654, and p3210 as follows: *
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* *
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* Upper double-word: *
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* *
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* 31 24 16 8 0 31 24 16 8 0 *
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* +----+----+----+----+ +----+----+----+----+ *
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* pFEDC | pF | pE | pD | pC | pBA98 | pB | pA | p9 | p8 | *
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* +----+----+----+----+ +----+----+----+----+ *
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* *
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* Lower double-word: *
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* *
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* 31 24 16 8 0 31 24 16 8 0 *
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* +----+----+----+----+ +----+----+----+----+ *
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* p7654 | p7 | p6 | p5 | p4 | p3210 | p3 | p2 | p1 | p0 | *
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* +----+----+----+----+ +----+----+----+----+ *
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* *
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* (Note that this diagram assumes a little endian memory *
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* configuration, although this kernel works equally well in *
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* either endian mode.) *
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* *
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* We compare these four words against a packed copy of the threshold *
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* value. The packed threshold contains four copies of the threshold *
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* value, one in each byte, like so: *
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* *
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* 31 24 16 8 0 *
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* +----+----+----+----+ *
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* thththth | th | th | th | th | *
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* +----+----+----+----+ *
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* *
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* We compare using MAXU4. This instruction with select the smaller *
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* value between our input pixels and the threshold value. The *
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* result is that input values below the threshold are clamped to the *
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* threshold value. *
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* *
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* The 16 results are then written with two STDWs. *
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* *
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* MEMORY NOTE *
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* This code is ENDIAN NEUTRAL. *
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* *
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* The input and output arrays must be double-word aligned. *
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* *
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* No bank conflicts occur, regardless of the relative alignment of *
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* in_data[] and out_data[]. *
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* *
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* CYCLES *
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* cycles = 0.125 * rows * cols + 20. *
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* For rows = 32 and cols = 32, cycles = 148. *
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* *
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* This number includes 6 cycles of function call overhead. The *
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* exact overhead will vary depending on compiler options used. *
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* *
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* CODESIZE *
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* 108 bytes. *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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.sect ".text:_thr_le2thr"
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.global _IMG_thr_le2thr
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_IMG_thr_le2thr:
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* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *
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.asg A4, A_i_ptr
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.asg B4, B_o_ptr
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.asg A6, A_rows
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.asg B6, B_cols
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.asg A8, A_th
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.asg B3, B_ret_addr
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.asg A3, A_i
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.asg A5, A_o_ptr
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.asg A6, A_t3210
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.asg A7, A_t7654
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.asg A8, A_thththth
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.asg A16, A_p3210
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.asg A17, A_p7654
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.asg B0, B_p
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.asg B5, B_i_ptr
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.asg B6, B_tBA98
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.asg B7, B_tFEDC
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.asg B8, B_pBA98
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.asg B9, B_pFEDC
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* ========================================================================= *
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* =========================== PIPE LOOP PROLOG ============================ *
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MPY .M1X A_rows, B_cols, A_i
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PACK2 A_th, A_th, A_thththth
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B .S2 loop ;[ 3,1]
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|| SHR A_i, 4, A_i
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ADD A_i_ptr, 8, B_i_ptr
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|| PACKL4 A_thththth, A_thththth, A_thththth
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|| SUB A_i, 2, A_i
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BDEC .S1 loop, A_i ;[ 3,2]
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|| LDDW .D1T1 *A_i_ptr++[2], A_p7654:A_p3210 ;[ 1,1]
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|| LDDW .D2T2 *B_i_ptr++[2], B_pFEDC:B_pBA98 ;[ 1,1]
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MVK 2, B_p
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; ===== 2 prolog stages collapsed
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* =========================== PIPE LOOP KERNEL ============================ *
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loop:
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MAXU4 .L1 A_p7654, A_thththth, A_t7654 ;[ 7,1]
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|| MAXU4 .L2X B_pBA98, A_thththth, B_tBA98 ;[ 7,1]
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|| BDEC .S1 loop, A_i ;[ 3,3]
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|| LDDW .D1T1 *A_i_ptr++[2], A_p7654:A_p3210 ;[ 1,4]
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|| LDDW .D2T2 *B_i_ptr++[2], B_pFEDC:B_pBA98 ;[ 1,4]
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[ B_p]SUB .S2 B_p, 1, B_p ;[ 8,1]
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||[ B_p]ADD .S1X B_o_ptr, 8, A_o_ptr
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||[!B_p]STDW .D2T1 A_t7654:A_t3210, *B_o_ptr++[2] ;[ 8,1]
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||[!B_p]STDW .D1T2 B_tFEDC:B_tBA98, *A_o_ptr++[2] ;[ 8,1]
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|| MAXU4 .L1 A_p3210, A_thththth, A_t3210 ;[ 6,2]
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|| MAXU4 .L2X B_pFEDC, A_thththth, B_tFEDC ;[ 6,2]
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* =========================== PIPE LOOP EPILOG ============================ *
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; ===== 2 epilog stages collapsed
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MAXU4 .L1 A_p7654, A_thththth, A_t7654 ;[ 7,4]
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|| MAXU4 .L2X B_pBA98, A_thththth, B_tBA98 ;[ 7,4]
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|| RETNOP B_ret_addr, 4
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STDW .D2T1 A_t7654:A_t3210, *B_o_ptr ;[ 8,4]
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|| STDW .D1T2 B_tFEDC:B_tBA98, *A_o_ptr ;[ 8,4]
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* ========================================================================= *
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* End of file: img_thr_le2thr.asm *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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