c6416
/
c6416_sdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

fix tvl320aci23.c spi_init 

Signed-off-by: surenyi <surenyi82@qq.com>
bfsk
surenyi 3 years ago
parent
c95a30ec4d
commit
80942dfa9d
1 changed files with 84 additions and 87 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Unified View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 171
      platforms/dsk/tlv320aic23.c

171
platforms/dsk/tlv320aic23.c
View File

@ -23,10 +23,10 @@ int mcbsp_spi_init()
MCBSP_SPCR_XRST_YES, // Transmitter reset(XRST) MCBSP_SPCR_XRST_YES, // Transmitter reset(XRST)
MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode
MCBSP_SPCR_RJUST_RZF, // Receive data sign-extension and MCBSP_SPCR_RJUST_RZF, // Receive data sign-extension and
// justification mode(RJUST) // justification mode(RJUST)
MCBSP_SPCR_CLKSTP_OF(2), // Clock stop(CLKSTP) mode: SPI mode without delay MCBSP_SPCR_CLKSTP_OF(2), // Clock stop(CLKSTP) mode: SPI mode without delay
MCBSP_SPCR_DXENA_OFF, // DX Enabler(DXENA) -Extra delay for MCBSP_SPCR_DXENA_OFF, // DX Enabler(DXENA) -Extra delay for
// DX turn-on time. // DX turn-on time.
MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode
MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR) MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR)
MCBSP_SPCR_RRST_YES // Receiver reset(RRST) MCBSP_SPCR_RRST_YES // Receiver reset(RRST)
@ -35,33 +35,33 @@ int mcbsp_spi_init()
mbconf.rcr = MCBSP_RCR_DEFAULT; mbconf.rcr = MCBSP_RCR_DEFAULT;
mbconf.xcr = MCBSP_XCR_RMK (//Transmit Control Register (XCR) mbconf.xcr = MCBSP_XCR_RMK (//Transmit Control Register (XCR)
MCBSP_XCR_XPHASE_SINGLE, // Transmit phases MCBSP_XCR_XPHASE_SINGLE, // Transmit phases
MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length
// in phase 2(XFRLEN2) // in phase 2(XFRLEN2)
MCBSP_XCR_XWDLEN2_16BIT, // Transmit element length MCBSP_XCR_XWDLEN2_16BIT, // Transmit element length
// in phase 2 // in phase 2
MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND) MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND)
MCBSP_XCR_XFIG_YES, // Transmit frame ignore(XFIG) MCBSP_XCR_XFIG_YES, // Transmit frame ignore(XFIG)
MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY) MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY)
MCBSP_XCR_XFRLEN1_OF(0), // Transmit frame length MCBSP_XCR_XFRLEN1_OF(0), // Transmit frame length
// in phase 1(XFRLEN1) // in phase 1(XFRLEN1)
MCBSP_XCR_XWDLEN1_16BIT, // Transmit element length MCBSP_XCR_XWDLEN1_16BIT, // Transmit element length
// in phase 1(XWDLEN1) // in phase 1(XWDLEN1)
MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature
); );
mbconf.srgr = MCBSP_SRGR_RMK( //serial port sample rate generator register(SRGR) mbconf.srgr = MCBSP_SRGR_RMK( //serial port sample rate generator register(SRGR)
MCBSP_SRGR_GSYNC_FREE, // Sample rate generator clock MCBSP_SRGR_GSYNC_FREE, // Sample rate generator clock
// synchronization(GSYNC). // synchronization(GSYNC).
MCBSP_SRGR_CLKSP_FALLING, // CLKS polarity clock edge select(CLKSP) MCBSP_SRGR_CLKSP_FALLING, // CLKS polarity clock edge select(CLKSP)
MCBSP_SRGR_CLKSM_INTERNAL, // MCBSP sample rate generator clock MCBSP_SRGR_CLKSM_INTERNAL, // MCBSP sample rate generator clock
// mode(CLKSM) // mode(CLKSM)
MCBSP_SRGR_FSGM_DXR2XSR, // Sample rate generator transmit frame MCBSP_SRGR_FSGM_DXR2XSR, // Sample rate generator transmit frame
// synchronization // synchronization
MCBSP_SRGR_FPER_OF(63), // Frame period(FPER) MCBSP_SRGR_FPER_OF(63), // Frame period(FPER)
MCBSP_SRGR_FWID_OF(31), // Frame width(FWID) MCBSP_SRGR_FWID_OF(31), // Frame width(FWID)
MCBSP_SRGR_CLKGDV_OF(15) // Sample rate generator clock MCBSP_SRGR_CLKGDV_OF(15) // Sample rate generator clock
// divider(CLKGDV) // divider(CLKGDV)
); );
mbconf.mcr = MCBSP_MCR_DEFAULT; mbconf.mcr = MCBSP_MCR_DEFAULT;
@ -77,18 +77,18 @@ int mcbsp_spi_init()
mbconf.xcere3 = MCBSP_XCERE3_DEFAULT; mbconf.xcere3 = MCBSP_XCERE3_DEFAULT;
mbconf.pcr = MCBSP_PCR_RMK( //serial port pin control register(PCR) mbconf.pcr = MCBSP_PCR_RMK( //serial port pin control register(PCR)
MCBSP_PCR_XIOEN_SP, // Transmitter in general-purpose I/O mode MCBSP_PCR_XIOEN_SP, // Transmitter in general-purpose I/O mode
MCBSP_PCR_RIOEN_GPIO, // Receiver in general-purpose I/O mode (XXX: no receive) MCBSP_PCR_RIOEN_GPIO, // Receiver in general-purpose I/O mode (XXX: no receive)
MCBSP_PCR_FSXM_INTERNAL, // Transmit frame synchronization mode MCBSP_PCR_FSXM_INTERNAL, // Transmit frame synchronization mode
MCBSP_PCR_FSRM_EXTERNAL, // Receive frame synchronization mode MCBSP_PCR_FSRM_EXTERNAL, // Receive frame synchronization mode
MCBSP_PCR_CLKXM_OUTPUT, // Transmitter clock mode (CLKXM) MCBSP_PCR_CLKXM_OUTPUT, // Transmitter clock mode (CLKXM)
MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM) MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM)
MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT) MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT)
MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT) MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT)
MCBSP_PCR_FSXP_ACTIVEHIGH, // Transmit frame synchronization polarity(FSXP) MCBSP_PCR_FSXP_ACTIVEHIGH, // Transmit frame synchronization polarity(FSXP)
MCBSP_PCR_FSRP_ACTIVEHIGH, // Receive frame synchronization polarity(FSRP) MCBSP_PCR_FSRP_ACTIVEHIGH, // Receive frame synchronization polarity(FSRP)
MCBSP_PCR_CLKXP_RISING, // Transmit clock polarity(CLKXP) MCBSP_PCR_CLKXP_RISING, // Transmit clock polarity(CLKXP)
MCBSP_PCR_CLKRP_FALLING // Receive clock polarity(CLKRP) MCBSP_PCR_CLKRP_FALLING // Receive clock polarity(CLKRP)
); );
__spi_handle = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); __spi_handle = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
@ -96,10 +96,9 @@ int mcbsp_spi_init()
MCBSP_config(__spi_handle, &mbconf); MCBSP_config(__spi_handle, &mbconf);
//Enable McBSP in steps //Enable McBSP in steps
MCBSP_start(__spi_handle, MCBSP_RCV_START | MCBSP_start(__spi_handle,
MCBSP_SRGR_START | MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
MCBSP_SRGR_FRAMESYNC, MCBSP_SRGR_DEFAULT_DELAY);
MCBSP_SRGR_DEFAULT_DELAY);
return 0; return 0;
} }
@ -155,10 +154,10 @@ int mcbsp_aic23_init()
MCBSP_SPCR_XRST_YES, // Transmitter reset(XRST) MCBSP_SPCR_XRST_YES, // Transmitter reset(XRST)
MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode MCBSP_SPCR_DLB_OFF, // Digital loopback(DLB) mode
MCBSP_SPCR_RJUST_RZF, // Receive data sign-extension and MCBSP_SPCR_RJUST_RZF, // Receive data sign-extension and
// justification mode(RJUST) // justification mode(RJUST)
MCBSP_SPCR_CLKSTP_OF(0), // Clock stop(CLKSTP) MCBSP_SPCR_CLKSTP_OF(0), // Clock stop(CLKSTP)
MCBSP_SPCR_DXENA_OFF, // DX Enabler(DXENA) -Extra delay for MCBSP_SPCR_DXENA_OFF, // DX Enabler(DXENA) -Extra delay for
// DX turn-on time. // DX turn-on time.
MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode MCBSP_SPCR_RINTM_RRDY, // Receive interrupt(RINT) mode
MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR) MCBSP_SPCR_RSYNCERR_NO, // Receive synchronization error(RSYNCERR)
MCBSP_SPCR_RRST_YES // Receiver reset(RRST) MCBSP_SPCR_RRST_YES // Receiver reset(RRST)
@ -167,33 +166,33 @@ int mcbsp_aic23_init()
mbconf.rcr = MCBSP_RCR_DEFAULT; mbconf.rcr = MCBSP_RCR_DEFAULT;
mbconf.xcr = MCBSP_XCR_RMK (//Transmit Control Register (XCR) mbconf.xcr = MCBSP_XCR_RMK (//Transmit Control Register (XCR)
MCBSP_XCR_XPHASE_SINGLE, // Transmit phases MCBSP_XCR_XPHASE_SINGLE, // Transmit phases
MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length MCBSP_XCR_XFRLEN2_OF(0), // Transmit frame length
// in phase 2(XFRLEN2) // in phase 2(XFRLEN2)
MCBSP_XCR_XWDLEN2_16BIT, // Transmit element length MCBSP_XCR_XWDLEN2_16BIT, // Transmit element length
// in phase 2 // in phase 2
MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND) MCBSP_XCR_XCOMPAND_MSB, // Transmit companding mode(XCOMPAND)
MCBSP_XCR_XFIG_YES, // Transmit frame ignore(XFIG) MCBSP_XCR_XFIG_YES, // Transmit frame ignore(XFIG)
MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY) MCBSP_XCR_XDATDLY_0BIT, // Transmit data delay(XDATDLY)
MCBSP_XCR_XFRLEN1_OF(0), // Transmit frame length MCBSP_XCR_XFRLEN1_OF(0), // Transmit frame length
// in phase 1(XFRLEN1) // in phase 1(XFRLEN1)
MCBSP_XCR_XWDLEN1_16BIT, // Transmit element length MCBSP_XCR_XWDLEN1_16BIT, // Transmit element length
// in phase 1(XWDLEN1) // in phase 1(XWDLEN1)
MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature MCBSP_XCR_XWDREVRS_DISABLE // Transmit 32-bit bit reversal feature
); );
mbconf.srgr = MCBSP_SRGR_RMK( //serial port sample rate generator register(SRGR) mbconf.srgr = MCBSP_SRGR_RMK( //serial port sample rate generator register(SRGR)
MCBSP_SRGR_GSYNC_FREE, // Sample rate generator clock MCBSP_SRGR_GSYNC_FREE, // Sample rate generator clock
// synchronization(GSYNC). // synchronization(GSYNC).
MCBSP_SRGR_CLKSP_FALLING, // CLKS polarity clock edge select(CLKSP) MCBSP_SRGR_CLKSP_FALLING, // CLKS polarity clock edge select(CLKSP)
MCBSP_SRGR_CLKSM_INTERNAL, // MCBSP sample rate generator clock MCBSP_SRGR_CLKSM_INTERNAL, // MCBSP sample rate generator clock
// mode(CLKSM) // mode(CLKSM)
MCBSP_SRGR_FSGM_DXR2XSR, // Sample rate generator transmit frame MCBSP_SRGR_FSGM_DXR2XSR, // Sample rate generator transmit frame
// synchronization // synchronization
MCBSP_SRGR_FPER_OF(63), // Frame period(FPER) MCBSP_SRGR_FPER_OF(63), // Frame period(FPER)
MCBSP_SRGR_FWID_OF(31), // Frame width(FWID) MCBSP_SRGR_FWID_OF(31), // Frame width(FWID)
MCBSP_SRGR_CLKGDV_OF(15) // Sample rate generator clock MCBSP_SRGR_CLKGDV_OF(15) // Sample rate generator clock
// divider(CLKGDV) // divider(CLKGDV)
); );
mbconf.mcr = MCBSP_MCR_DEFAULT; mbconf.mcr = MCBSP_MCR_DEFAULT;
@ -209,18 +208,18 @@ int mcbsp_aic23_init()
mbconf.xcere3 = MCBSP_XCERE3_DEFAULT; mbconf.xcere3 = MCBSP_XCERE3_DEFAULT;
mbconf.pcr = MCBSP_PCR_RMK( //serial port pin control register(PCR) mbconf.pcr = MCBSP_PCR_RMK( //serial port pin control register(PCR)
MCBSP_PCR_XIOEN_SP, // Transmitter in general-purpose I/O mode MCBSP_PCR_XIOEN_SP, // Transmitter in general-purpose I/O mode
MCBSP_PCR_RIOEN_SP, // Receiver in general-purpose I/O mode (XXX: no receive) MCBSP_PCR_RIOEN_SP, // Receiver in general-purpose I/O mode (XXX: no receive)
MCBSP_PCR_FSXM_INTERNAL, // Transmit frame synchronization mode MCBSP_PCR_FSXM_INTERNAL, // Transmit frame synchronization mode
MCBSP_PCR_FSRM_INTERNAL, // Receive frame synchronization mode MCBSP_PCR_FSRM_INTERNAL, // Receive frame synchronization mode
MCBSP_PCR_CLKXM_OUTPUT, // Transmitter clock mode (CLKXM) MCBSP_PCR_CLKXM_OUTPUT, // Transmitter clock mode (CLKXM)
MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM) MCBSP_PCR_CLKRM_INPUT, // Receiver clock mode (CLKRM)
MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT) MCBSP_PCR_CLKSSTAT_0, // CLKS pin status(CLKSSTAT)
MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT) MCBSP_PCR_DXSTAT_0, // DX pin status(DXSTAT)
MCBSP_PCR_FSXP_ACTIVEHIGH, // Transmit frame synchronization polarity(FSXP) MCBSP_PCR_FSXP_ACTIVEHIGH, // Transmit frame synchronization polarity(FSXP)
MCBSP_PCR_FSRP_ACTIVEHIGH, // Receive frame synchronization polarity(FSRP) MCBSP_PCR_FSRP_ACTIVEHIGH, // Receive frame synchronization polarity(FSRP)
MCBSP_PCR_CLKXP_RISING, // Transmit clock polarity(CLKXP) MCBSP_PCR_CLKXP_RISING, // Transmit clock polarity(CLKXP)
MCBSP_PCR_CLKRP_RISING // Receive clock polarity(CLKRP) MCBSP_PCR_CLKRP_RISING // Receive clock polarity(CLKRP)
); );
__aic23_handle = MCBSP_open(MCBSP_DEV2, MCBSP_OPEN_RESET); __aic23_handle = MCBSP_open(MCBSP_DEV2, MCBSP_OPEN_RESET);
@ -228,11 +227,9 @@ int mcbsp_aic23_init()
MCBSP_config(__aic23_handle, &mbconf); MCBSP_config(__aic23_handle, &mbconf);
//Enable McBSP in steps //Enable McBSP in steps
MCBSP_start(__aic23_handle, MCBSP_RCV_START | MCBSP_start(__aic23_handle,
MCBSP_SRGR_START | MCBSP_RCV_START | MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC,
MCBSP_XMIT_START | MCBSP_SRGR_DEFAULT_DELAY);
MCBSP_SRGR_FRAMESYNC,
MCBSP_SRGR_DEFAULT_DELAY);
return 0; return 0;
} }

Write Preview
Loading…
Cancel
Save