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261 lines
15 KiB
261 lines
15 KiB
;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* DSPLIB DSP Signal Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.8 Sun Sep 29 03:32:17 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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* ========================================================================= *
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* NAME *
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* DSP_bexp -- Block exponent of a vector *
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* *
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* REVISION DATE *
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* 12-Jul-2001 *
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* *
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* USAGE *
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* This routine has the following C prototype: *
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* *
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* int DSP_bexp *
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* ( *
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* const int *x, /* Input Data */ *
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* unsigned nx /* Number of elements */ *
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* ); *
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* *
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* The DSP_bexp routine accepts a list of 'num' input points and *
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* performs the determination of the block exponent. It returns *
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* the minimum number of "redundant sign bits" observed on the *
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* block of data. *
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* *
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* DESCRIPTION *
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* The DSP_bexp function, performs a determination of the block *
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* exponent of the vector of elements and returns the maximum *
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* exponent. This information can then be used to re-normalize *
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* the vector. This operation is useful when auto-scaling is *
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* required as in a FFT. The DSP_bexp operation returns the minimum *
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* norm of the vector. The minimum norm corresponds to the *
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* maximum exponent. *
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* *
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* C CODE *
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* The following is a general C code description of the algorithm *
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* without restrictions. This implementation may have restrictions *
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* as noted under 'ASSUMPTIONS' below. *
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* *
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* int DSP_bexp(const int *x, short nx) *
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* { *
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* int i; *
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* int mask, mag; *
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* *
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* mask = 0; *
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* *
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* /* ---------------------------------------------------- */ *
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* /* Merge the absolute values of all the elements */ *
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* /* together. The leftmost bit-change on this mask */ *
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* /* gives us the magnitude we desire. */ *
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* /* ---------------------------------------------------- */ *
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* for (i = 0; i < nx; i++) *
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* mask |= x[i] ^ (x[i] >> 31); *
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* *
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* /* ---------------------------------------------------- */ *
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* /* Find the magnitude of the mask. */ *
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* /* ---------------------------------------------------- */ *
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* for (mag = 0; (1 << mag) < mask; mag++) *
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* ; *
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* *
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* return 31 - mag; *
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* } *
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* *
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* ASSUMPTIONS *
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* nx >= 8. *
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* nx % 8 == 0. *
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* *
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* The array 'x' is double-word aligned. *
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* *
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* NOTES *
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* This code is interrupt tolerant, but not interruptible. It masks *
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* interrupts for its entire duration with branch delay slots. *
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* *
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* This code is ENDIAN NEUTRAL. *
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* *
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* SOURCE *
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* DSPLIB. *
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* *
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* CYCLES *
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* cycles = nx/2 + 21, including 6 cycle function call overhead. *
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* For nx = 32, cycles = 37. *
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* *
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* CODESIZE *
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* 236 bytes. *
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* *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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.sect ".text:_bexp"
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.global _DSP_bexp
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_DSP_bexp:
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* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *
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.asg A4, A_x
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.asg B4, B_nx
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.asg B3, B_ret_addr
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.asg A4, A_ret_val
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.asg B0, B_i
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.asg A0, A_p
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.asg B17, B_x
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.asg A9, A_x7
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.asg A8, A_x6
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.asg B9, B_x5
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.asg B8, B_x4
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.asg A7, A_x3
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.asg A6, A_x2
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.asg B7, B_x1
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.asg B6, B_x0
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.asg A16, A_k31
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.asg A18, A_a7
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.asg A17, A_a6
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.asg B16, B_k31
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.asg B19, B_a5
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.asg B18, B_a4
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.asg A18, A_a3
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.asg A17, A_a2
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.asg B19, B_a1
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.asg B18, B_a0
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.asg A9, A_b7
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.asg A17, A_b6
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.asg B9, B_b5
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.asg B18, B_b4
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.asg A7, A_b3
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.asg A17, A_b2
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.asg B7, B_b1
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.asg B18, B_b0
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.asg A5, A_m
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.asg B5, B_m
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* ========================================================================= *
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* =========================== PIPE LOOP PROLOG ============================ *
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B .S1 loop
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|| MVK .L1 2, A_p
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|| ADD .L2X A_x, 8, B_x
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|| SHR .S2 B_nx, 3, B_i
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|| ZERO .D1 A_m
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|| ZERO .D2 B_m
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LDDW .D1T2 *A_x[2], B_x5:B_x4 ;[ 1,1]
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|| LDDW .D2T1 *B_x[2], A_x7:A_x6 ;[ 1,1]
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|| MVK .S1 31, A_k31
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|| MVK .S2 31, B_k31
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|| SUB .L2 B_i, 1, B_i
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; ===== 2 stages of prolog collapsed
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* =========================== PIPE LOOP KERNEL ============================ *
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loop:
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[!A_p]OR .S2 B_b4, B_m, B_m ;[10,1]
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||[!A_p]OR .S1 A_b6, A_m, A_m ;[10,1]
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|| XOR .D2 B_x1, B_a1, B_b1 ;[10,1]
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|| XOR .D1 A_x3, A_a3, A_b3 ;[10,1]
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|| SSHVR .M2 B_x5, B_k31, B_a5 ;[ 6,2]
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|| SSHVR .M1 A_x7, A_k31, A_a7 ;[ 6,2]
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[!A_p]OR .L2 B_b1, B_m, B_m ;[11,1]
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||[!A_p]OR .S1 A_b3, A_m, A_m ;[11,1]
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|| XOR .S2 B_x0, B_a0, B_b0 ;[11,1]
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|| XOR .L1 A_x2, A_a2, A_b2 ;[11,1]
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|| SSHVR .M2 B_x4, B_k31, B_a4 ;[ 7,2]
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|| SSHVR .M1 A_x6, A_k31, A_a6 ;[ 7,2]
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|| LDDW .D1T2 *A_x++[4], B_x1:B_x0 ;[ 3,3]
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|| LDDW .D2T1 *B_x++[4], A_x3:A_x2 ;[ 3,3]
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[!A_p]OR .L2 B_b0, B_m, B_m ;[12,1]
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||[!A_p]OR .D1 A_b2, A_m, A_m ;[12,1]
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||[ B_i]BDEC .S2 loop, B_i ;[ 8,2]
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||[ A_p]SUB .L1 A_p, 1, A_p ;[ 8,2]
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|| XOR .D2 B_x5, B_a5, B_b5 ;[ 8,2]
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|| XOR .S1 A_x7, A_a7, A_b7 ;[ 8,2]
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|| SSHVR .M2 B_x1, B_k31, B_a1 ;[ 8,2]
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|| SSHVR .M1 A_x3, A_k31, A_a3 ;[ 8,2]
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[!A_p]OR .S2 B_b5, B_m, B_m ;[ 9,2]
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||[!A_p]OR .L1 A_b7, A_m, A_m ;[ 9,2]
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|| XOR .L2 B_x4, B_a4, B_b4 ;[ 9,2]
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|| XOR .S1 A_x6, A_a6, A_b6 ;[ 9,2]
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|| SSHVR .M2 B_x0, B_k31, B_a0 ;[ 9,2]
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|| SSHVR .M1 A_x2, A_k31, A_a2 ;[ 9,2]
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|| LDDW .D1T2 *A_x[2], B_x5:B_x4 ;[ 1,4]
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|| LDDW .D2T1 *B_x[2], A_x7:A_x6 ;[ 1,4]
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* =========================== PIPE LOOP EPILOG ============================ *
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; ===== 2 stages of epilog collasped
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OR .L2 B_b4, B_m, B_m ;[10,4]
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|| OR .S1 A_b6, A_m, A_m ;[10,4]
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|| XOR .D2 B_x1, B_a1, B_b1 ;[10,4]
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|| XOR .D1 A_x3, A_a3, A_b3 ;[10,4]
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|| RET .S2 B_ret_addr
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OR .L2 B_b1, B_m, B_m ;[11,4]
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|| OR .S1 A_b3, A_m, A_m ;[11,4]
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|| XOR .S2 B_x0, B_a0, B_b0 ;[11,4]
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|| XOR .L1 A_x2, A_a2, A_b2 ;[11,4]
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OR .L2 B_b0, B_m, B_m ;[12,4]
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OR .D1 A_b2, A_m, A_m ;[12,4]
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OR .L1X A_m, B_m, A_m
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NORM .L1 A_m, A_ret_val
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* ========================================================================= *
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* End of file: dsp_bexp.asm *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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