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853 lines
52 KiB
853 lines
52 KiB
;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* DSPLIB DSP Signal Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.6 Sun Sep 29 03:32:21 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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*========================================================================== *
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* TEXAS INSTRUMENTS, INC. *
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* *
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* NAME *
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* DSP_fft32x32s: Double Precision FFT with scaling *
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* *
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* USAGE *
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* This routine is C-callable and can be called as: *
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* *
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* void DSP_fft32x32s(const int * ptr_w, int npoints, *
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* int * ptr_x, int * ptr_y ) ; *
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* *
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* ptr_w = input twiddle factors *
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* npoints = number of points *
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* ptr_x = transformed data reversed *
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* ptr_y = linear transformed data *
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* *
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* (See the C compiler reference guide.) *
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* *
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* DESCRIPTION *
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* The following code performs a mixed radix FFT for "npoints" which *
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* is either a multiple of 4 or 2. It uses logN4 - 1 stages of radix4 *
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* transform and performs either a radix2 or radix4 transform on the *
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* last stage depending on "npoints". If "npoints" is a multiple of 4, *
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* then this last stage is also a radix4 transform, otherwise it is a *
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* radix2 transform. This program is available as a C compilable file *
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* to automatically generate the twiddle factors "twiddle_split.c" *
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* *
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* Generate special vector of twiddle factors *
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* *
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* for (j=1, k=0; j < npoints>>2; j = j <<2 ) *
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* { *
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* for (i=0; i < npoints>>2; i += j) *
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* { *
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* theta1 = 2*PI*i/npoints; *
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* x_t = M*cos(theta1); *
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* y_t = M*sin(theta1); *
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* ptr_w[k+1] = (int) x_t; *
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* if (x_t >= M) ptr_w[k+1] = 0x7fffffff; *
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* ptr_w[k+0] = (int) y_t; *
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* if (y_t >= M) ptr_w[k+0] = 0x7fffffff; *
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* *
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* theta2 = 4*PI*i/npoints; *
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* x_t = M*cos(theta2); *
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* y_t = M*sin(theta2); *
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* ptr_w[k+3] = (int) x_t; *
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* *
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* if (x_t >= M) ptr_w[k+3] = 0x7fffffff; *
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* ptr_w[k+2] = (int) y_t; *
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* if (y_t >= M) ptr_w[k+2] = 0x7fffffff; *
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* *
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* theta3 = 6*PI*i/npoints; *
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* x_t = M*cos(theta3); *
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* y_t = M*sin(theta3); *
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* ptr_w[k+5] = (int) x_t; *
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* if (x_t >= M) ptr_w[k+5] = 0x7fffffff; *
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* ptr_w[k+4] = (int) y_t; *
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* if (y_t >= M) ptr_w[k+4] = 0x7fffffff; *
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* k += 6; *
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* } *
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* } *
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* *
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* *
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* ASSUMPTIONS *
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* This code works for both "npoints" a multiple of 2 or 4. *
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* The arrays 'x[]', 'y[]', and 'w[]' all must be aligned on a *
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* double-word boundary for the "optimized" implementations. *
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* The input and output data are complex, with the real/imaginary *
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* components stored in adjacent locations in the array. The real *
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* components are stored at even array indices, and the imaginary *
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* components are stored at odd array indices. The input, twiddle *
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* factors are in 32 bit precision. The 32 by 32 multiplies are *
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* done with a 1.5 bit loss in accuracy. This comes about because *
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* the contribution of the low sixteen bits to the 32 bit result *
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* is not computed. In addition the contribution of the low * high *
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* term is shifted by 16 as opposed to 15, for a loss 0f 0.5 bits *
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* after rounding. To illustrate real part of complex multiply of: *
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* (X + jY) ( C + jS) = *
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* *
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* _mpyhir(si10 , yt1_0) + _mpyhir(co10 , xt1_0) + *
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* (((MPYLUHS(si10,yt1_0) + MPYLUHS(co10, xt1_0) *
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* + 0x8000) >> 16) << 1) *
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* *
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* The intrinsic C version of this code performs this function as: *
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* *
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* _mpyhir(si10 , yt1_0) + _mpyhir(co10 , xt1_0) + *
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* (_dotprsu2(yt1_0xt1_0, si10co10) << 1); *
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* *
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* *
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* where the functions _mpyhir, MPYLUHS are as follows: *
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* *
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* #define _mpyhir(x,y) \ *
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* (((int)((short)(x>>16)*(unsigned short)(y&0x0000FFFF)+0x4000) >> 15) *
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* + \ ((int)((short)(x >> 16) * (short)((y) >> 16)) << 1)) *
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* *
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* #define MPYLUHS(x,y) \ *
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* ( (int) ((unsigned short)(x & 0x0000FFFF) * (short) (y >> 16)) ) *
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* *
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* *
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* TECHNIQUES *
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* The following C code represents an implementation of the Cooley *
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* Tukey radix 4 DIF FFT. It accepts the inputs in normal order and *
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* produces the outputs in digit reversed order. The natural C code *
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* shown in this file on the other hand, accepts the inputs in nor- *
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* mal order and produces the outputs in normal order. *
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* *
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* Several transformations have been applied to the original Cooley *
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* Tukey code to produce the natural C code description shown here. *
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* In order to understand these it would first be educational to *
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* understand some of the issues involved in the conventional Cooley *
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* Tukey FFT code. *
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* *
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* void radix4(int n, short x[], short wn[]) *
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* { *
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* int n1, n2, ie, ia1, ia2, ia3; *
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* int i0, i1, i2, i3, i, j, k; *
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* short co1, co2, co3, si1, si2, si3; *
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* short xt0, yt0, xt1, yt1, xt2, yt2; *
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* short xh0, xh1, xh20, xh21, xl0, xl1,xl20,xl21; *
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* *
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* n2 = n; *
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* ie = 1; *
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* for (k = n; k > 1; k >>= 2) *
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* { *
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* n1 = n2; *
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* n2 >>= 2; *
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* ia1 = 0; *
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* *
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* for (j = 0; j < n2; j++) *
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* { *
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* ia2 = ia1 + ia1; *
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* ia3 = ia2 + ia1; *
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* *
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* co1 = wn[2 * ia1 ]; *
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* si1 = wn[2 * ia1 + 1]; *
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* co2 = wn[2 * ia2 ]; *
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* si2 = wn[2 * ia2 + 1]; *
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* co3 = wn[2 * ia3 ]; *
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* si3 = wn[2 * ia3 + 1]; *
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* ia1 = ia1 + ie; *
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* *
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* for (i0 = j; i0< n; i0 += n1) *
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* { *
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* i1 = i0 + n2; *
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* i2 = i1 + n2; *
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* i3 = i2 + n2; *
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* *
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* *
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* xh0 = x[2 * i0 ] + x[2 * i2 ]; *
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* xh1 = x[2 * i0 + 1] + x[2 * i2 + 1]; *
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* xl0 = x[2 * i0 ] - x[2 * i2 ]; *
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* xl1 = x[2 * i0 + 1] - x[2 * i2 + 1]; *
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* *
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* xh20 = x[2 * i1 ] + x[2 * i3 ]; *
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* xh21 = x[2 * i1 + 1] + x[2 * i3 + 1]; *
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* xl20 = x[2 * i1 ] - x[2 * i3 ]; *
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* xl21 = x[2 * i1 + 1] - x[2 * i3 + 1]; *
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* *
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* x[2 * i0 ] = xh0 + xh20; *
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* x[2 * i0 + 1] = xh1 + xh21; *
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* *
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* xt0 = xh0 - xh20; *
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* yt0 = xh1 - xh21; *
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* xt1 = xl0 + xl21; *
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* yt2 = xl1 + xl20; *
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* xt2 = xl0 - xl21; *
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* yt1 = xl1 - xl20; *
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* *
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* x[2 * i1 ] = (xt1 * co1 + yt1 * si1) >> 15; *
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* x[2 * i1 + 1] = (yt1 * co1 - xt1 * si1) >> 15; *
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* x[2 * i2 ] = (xt0 * co2 + yt0 * si2) >> 15; *
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* x[2 * i2 + 1] = (yt0 * co2 - xt0 * si2) >> 15; *
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* x[2 * i3 ] = (xt2 * co3 + yt2 * si3) >> 15; *
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* x[2 * i3 + 1] = (yt2 * co3 - xt2 * si3) >> 15; *
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* } *
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* } *
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* *
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* ie <<= 2; *
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* } *
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* } *
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* *
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* The conventional Cooley Tukey FFT, is written using three loops. *
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* The outermost loop "k" cycles through the stages. There are log *
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* N to the base 4 stages in all. The loop "j" cycles through the *
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* groups of butterflies with different twiddle factors, loop "i" *
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* reuses the twiddle factors for the different butterflies within *
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* a stage. It is interesting to note the following: *
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* *
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*-------------------------------------------------------------------------- *
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* Stage# #Groups # Butterflies with common #Groups*Bflys *
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* twiddle factors *
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*-------------------------------------------------------------------------- *
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* 1 N/4 1 N/4 *
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* 2 N/16 4 N/4 *
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* .. *
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* logN 1 N/4 N/4 *
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*-------------------------------------------------------------------------- *
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* *
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* The following statements can be made based on above observations: *
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* *
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* a) Inner loop "i0" iterates a veriable number of times. In *
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* particular the number of iterations quadruples every time from *
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* 1..N/4. Hence software pipelining a loop that iterates a vraiable *
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* number of times is not profitable. *
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* *
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* b) Outer loop "j" iterates a variable number of times as well. *
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* However the number of iterations is quartered every time from *
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* N/4 . . Hence the behaviour in (a) and (b) are exactly opposite *
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* to each other. *
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* *
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* c) If the two loops "i" and "j" are colaesced together then they *
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* will iterate for a fixed number of times namely N/4. This allows *
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* us to combine the "i" and "j" loops into 1 loop. Optimized impl- *
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* ementations will make use of this fact. *
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* *
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* In addition the Cooley Tukey FFT accesses three twiddle factors *
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* per iteration of the inner loop, as the butterflies that re-use *
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* twiddle factors are lumped together. This leads to accessing the *
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* twiddle factor array at three points each sepearted by "ie". Note *
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* that "ie" is initially 1, and is quadrupled with every iteration. *
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* Therfore these three twiddle factors are not even contiguous in *
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* the array. *
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* *
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* In order to vectorize the FFT, it is desirable to access twiddle *
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* factor array using double word wide loads and fetch the twiddle *
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* factors needed. In order to do this a modified twiddle factor *
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* array is created, in which the factors WN/4, WN/2, W3N/4 are *
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* arranged to be contiguous. This eliminates the seperation between *
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* twiddle factors within a butterfly. However this implies that as *
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* the loop is traversed from one stage to another, that we maintain *
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* a redundant version of the twiddle factor array. Hence the size *
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* of the twiddle factor array increases as compared to the normal *
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* Cooley Tukey FFT. The modified twiddle factor array is of size *
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* "2 * N" where the conventional Cooley Tukey FFT is of size"3N/4" *
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* where N is the number of complex points to be transformed. The *
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* routine that generates the modified twiddle factor array was *
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* presented earlier. With the above transformation of the FFT, *
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* both the input data and the twiddle factor array can be accessed *
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* using double-word wide loads to enable packed data processing. *
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* *
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* The final stage is optimised to remove the multiplication as *
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* w0 = 1. This stage also performs digit reversal on the data, *
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* so the final output is in natural order. *
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* *
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* The fft() code shown here performs the bulk of the computation *
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* in place. However, because digit-reversal cannot be performed *
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* in-place, the final result is written to a separate array, y[]. *
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* *
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* There is one slight break in the flow of packed processing that *
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* needs to be comprehended. The real part of the complex number is *
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* in the lower half, and the imaginary part is in the upper half. *
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* The flow breaks in case of "xl0" and "xl1" because in this case *
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* the real part needs to be combined with the imaginary part because *
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* of the multiplication by "j". This requires a packed quantity like *
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* "xl21xl20" to be rotated as "xl20xl21" so that it can be combined *
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* using add2's and sub2's. Hence the natural version of C code *
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* shown below is transformed using packed data processing as shown: *
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* *
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* xl0 = x[2 * i0 ] - x[2 * i2 ]; *
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* xl1 = x[2 * i0 + 1] - x[2 * i2 + 1]; *
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* xl20 = x[2 * i1 ] - x[2 * i3 ]; *
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* xl21 = x[2 * i1 + 1] - x[2 * i3 + 1]; *
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* *
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* xt1 = xl0 + xl21; *
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* yt2 = xl1 + xl20; *
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* xt2 = xl0 - xl21; *
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* yt1 = xl1 - xl20; *
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* *
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* xl1_xl0 = _sub2(x21_x20, x21_x20) *
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* xl21_xl20 = _sub2(x32_x22, x23_x22) *
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* xl20_xl21 = _rotl(xl21_xl20, 16) *
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* *
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* yt2_xt1 = _add2(xl1_xl0, xl20_xl21) *
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* yt1_xt2 = _sub2(xl1_xl0, xl20_xl21) *
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* *
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* Also notice that xt1, yt1 endup on seperate words, these need to *
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* be packed together to take advantage of the packed twiddle fact *
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* ors that have been loaded. In order for this to be achieved they *
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* are re-aligned as follows: *
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* *
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* yt1_xt1 = _packhl2(yt1_xt2, yt2_xt1) *
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* yt2_xt2 = _packhl2(yt2_xt1, yt1_xt2) *
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* *
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* In the folllowing code since all data elements are 32 bits, add2 *
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* sub2 are replaced with normal 32 bit add's and subtracts. *
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* The packed words "yt1_xt1" allows the loaded"sc" twiddle factor *
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* to be used for the complex multiplies. The real part of the *
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* multiply and the imaginary part of the multiply are performed *
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* as 16x32 multiplies using MPYLIR and MPYHIR *
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* *
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* (X + jY) ( C + j S) = (XC + YS) + j (YC - XS). *
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* *
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* The actual twiddle factors for the FFT are cosine, - sine. The *
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* twiddle factors stored in the table are csine and sine, hence *
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* the sign of the "sine" term is comprehended during multipli- *
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* cation as shown above. *
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* *
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* MEMORY NOTE *
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* The optimized implementations are written for LITTLE ENDIAN. *
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* *
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* CYCLES *
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* [(N/4 + 1) * 10 + 10] * ceil(log4(N) - 1) + 6 * (N/4 + 2) + 27 *
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* *
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* N = 512, [1290 + 10] * 4 + 6 * 130 + 27 = 6007 cycles *
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* *
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* CODESIZE *
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* 932 bytes *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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|
* All Rights Reserved. *
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* ========================================================================= *
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.sect ".data:copyright_h"
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*============================================================================*
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.sect ".text:_fft32x32s"
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.global _DSP_fft32x32s
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_DSP_fft32x32s:
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*================== SYMBOLIC REGISTER ASSIGNMENTS: SETUP ======================*
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.asg B15, B_SP ; Stack pointer, B datapath
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.asg A31, A_SP ; Stack pointer, A datapath
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.asg B0, B_csr ; CSR's value
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.asg B1, B_no_gie ; CSR w/ GIE bit cleared
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.asg A0, A_csr ; Copy of CSR's value
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.asg B3, B_ret ; Return address
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.asg A0, A_whl
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; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
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.asg A4, A_ptr_w
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.asg B4, B_n
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.asg A6, A_ptr_x
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.asg B6, B_ptr_y
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.asg A15, A_stride
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.asg A13, A_tw_offset
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.asg A14, A_radix
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.asg B0, B_radix2
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.asg A17, A_j
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.asg A23, A_fft_jmp
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.asg B19, B_fft_jmp
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.asg A19, A_h2
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.asg A18, A_l1
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.asg A20, A_l2
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.asg B5, B_l1
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.asg B20, B_h2
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.asg B21, B_l2
|
|
.asg A11, A_x
|
|
.asg A21, A_w0
|
|
.asg B18, B_w1
|
|
.asg A22, A_w2
|
|
.asg A3, A_fft_jmp_1
|
|
.asg B3, B_i
|
|
.asg B1, B_pro
|
|
.asg A1, A_pro
|
|
; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
|
|
.asg A11, A_x
|
|
.asg A18, A_l1
|
|
.asg A19, A_h2
|
|
.asg A20, A_l2
|
|
.asg A21, A_w0
|
|
.asg B18, B_w1
|
|
.asg A22, A_w2
|
|
.asg A17, A_j
|
|
.asg A23, A_fft_jmp
|
|
.asg B19, B_fft_jmp
|
|
.asg B5, B_l1
|
|
.asg B20, B_h2
|
|
.asg B21, B_l2
|
|
.asg B3, B_i
|
|
.asg B1, B_pro
|
|
.asg B29, B_xp1
|
|
.asg B28, B_xp0
|
|
.asg A25, A_xl1p1
|
|
.asg A24, A_xl1p0
|
|
.asg B23, B_xh2p1
|
|
.asg B22, B_xh2p0
|
|
.asg A27, A_xl2p1
|
|
.asg A26, A_xl2p0
|
|
.asg A8, A_xh0
|
|
.asg A25, A_xh1
|
|
.asg B7, B_xl0
|
|
.asg B10, B_xl1
|
|
.asg A5, A_xh20
|
|
.asg A9, A_xh21
|
|
.asg B9, B_xl20
|
|
.asg B22, B_xl21
|
|
.asg A26, A_y_h1_0
|
|
.asg A27, A_y_h1_1
|
|
.asg B7, B_j
|
|
.asg B31, B_co10
|
|
.asg B30, B_si10
|
|
.asg A31, A_co20
|
|
.asg A30, A_si20
|
|
.asg B27, B_co30
|
|
.asg B26, B_si30
|
|
.asg A9, A_xt0
|
|
.asg A5, A_yt0
|
|
.asg B8, B_xt1
|
|
.asg B24, B_yt2
|
|
.asg B25, B_xt2
|
|
.asg B16, B_yt1
|
|
.asg B26, B_co10si10
|
|
.asg A7, A_co20si20
|
|
.asg B26, B_co30si30
|
|
.asg B8, B_si10co10
|
|
.asg A29, A_si20co20
|
|
.asg B9, B_si30co30
|
|
.asg A10, A_yt0xt0
|
|
.asg B9, B_yt1xt1
|
|
.asg B22, B_yt2xt2
|
|
.asg A7, A_si10
|
|
.asg B2, B_p0r
|
|
.asg A24, A_p1r
|
|
.asg B24, B_y_h2_0
|
|
.asg B7, B_p01r
|
|
.asg B10, B_p0c
|
|
.asg A2, A_p1c
|
|
.asg B25, B_y_h2_1
|
|
.asg B23, B_p01c
|
|
.asg A3, A_p2r
|
|
.asg A28, A_p3r
|
|
.asg A28, A_y_l1_0
|
|
.asg A3, A_p23r
|
|
.asg A3, A_p2c
|
|
.asg A7, A_p3c
|
|
.asg A29, A_y_l1_1
|
|
.asg A3, A_p23c
|
|
.asg B8, B_p4r
|
|
.asg B0, B_p5r
|
|
.asg B28, B_y_l2_0
|
|
.asg B30, B_p45r
|
|
.asg B2, B_p4c
|
|
.asg B27, B_p5c
|
|
.asg B29, B_y_l2_1
|
|
.asg B16, B_p45c
|
|
.asg A16, A_x_1
|
|
.asg B17, B_x__
|
|
.asg A0, A_ifj
|
|
; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
|
|
; Stack frame. 14 words: A10..A15, B10..B14, B3, CSR, pad
|
|
;-
|
|
STW .D2T1 A15, *B_SP--[14] ; Save A15
|
|
|
|
MV .S1X B_SP, A_SP ; Twin Stack
|
|
|
|
STW .D1T1 A14, *+A_SP[12] ; Save A14
|
|
|| STW .D2T2 B14, *+B_SP[11] ; Save B14
|
|
|| MVC .S2 CSR, B_csr ; CSR's
|
|
|
|
STW .D1T1 A13, *+A_SP[10] ; Save A13
|
|
|| STW .D2T2 B13, *+B_SP[ 9] ; Save B13
|
|
|| AND .L2 B_csr, -2, B_no_gie ; Clear GIE
|
|
;-
|
|
STW .D1T1 A12, *+A_SP[ 8] ; Save A12
|
|
|| STW .D2T2 B12, *+B_SP[ 7] ; Save B12
|
|
|
|
STW .D1T1 A11, *+A_SP[ 6] ; Save A11
|
|
|| STW .D2T2 B11, *+B_SP[ 5] ; Save B11
|
|
|| MV .L1X B_csr, A_csr ; Part. MV
|
|
|| NORM .L2 B_n, B_radix2 ;[ 2,0]
|
|
|
|
STW .D1T1 A10, *+A_SP[ 4] ; Save A10
|
|
|| STW .D2T2 B10, *+B_SP[ 3] ; Save B10
|
|
|| MVC .S2 B_no_gie, CSR ; Disable int.
|
|
|| AND .L2 B_radix2, 1, B_radix2 ;_norm(n)& 1
|
|
|| MVK .S1 4, A_radix ;radix = 4?
|
|
|| ZERO .L1 A_tw_offset ;tw_offset = 0;
|
|
|
|
; ===== Interrupts masked here =====
|
|
|
|
STW .D1T1 A_csr, *+A_SP[ 2] ; Save CSR
|
|
|| STW .D2T2 B_ret, *+B_SP[ 1] ; return
|
|
||[ B_radix2]MVK.L1 2, A_radix ;radix = 2
|
|
|| MV .S1X B_n, A_stride ;stride=n
|
|
; ============================ PIPE LOOP PROLOG ==============================
|
|
ADDAH .D1 A_ptr_w, A_tw_offset,A_w0 ;
|
|
|| SHRU .S1 A_stride, 2, A_h2 ;[ 6,0]
|
|
|
|
ADDAH .D1 A_h2, A_h2, A_l2 ;[ 7,0]
|
|
|| MVK .L1 1, A_pro ;
|
|
|| MVK .L2 1, B_pro ;[11,0]
|
|
|
|
ADD .L2X A_w0, 8, B_w1 ;[ 8,0]
|
|
|| MPYSU .M1 6, A_stride, A_fft_jmp ;
|
|
|| SHRU .S1 A_stride, 1, A_l1 ;[10,0]
|
|
|
|
MV .D2X A_l2, B_l2 ;[ 9,0]
|
|
|| SHL .S2 B_pro, 30, B_pro ;[11,0]
|
|
|| LDDW .D1T1 *A_ptr_x[A_l1], A_xl1p1:A_xl1p0 ;
|
|
|
|
LOOP_WHILE:
|
|
|
|
SHRU .S2 B_n, 2, B_i ;[10,0]
|
|
|| MV .L2X A_h2, B_h2 ;[10,0]
|
|
|| ROTL .M1 A_ptr_x, 0, A_x ;
|
|
|| LDDW .D1T2 *A_ptr_x[0], B_xp1:B_xp0 ;
|
|
|
|
SHRU .S2X A_fft_jmp, 3, B_fft_jmp ;[11,0]
|
|
|| SHRU .S1 A_fft_jmp, 1, A_fft_jmp_1 ;[11,0]
|
|
|| MPYSU .M1 0, A_j, A_j ;[11,0]
|
|
|| ADD .L1X B_w1, 8, A_w2 ;[12,0]
|
|
|| LDDW .D1T2 *A_ptr_x[A_h2], B_xh2p1:B_xh2p0 ;
|
|
|
|
SUB .D2 B_i, 1, B_i ;[12,0]
|
|
|| MV .S2X A_l1, B_l1 ;[12,0]
|
|
|| SUB .L2 B_fft_jmp, 3, B_fft_jmp ;[12,0]
|
|
|| ADD .L1 A_tw_offset,A_fft_jmp_1,A_tw_offset ;
|
|
|| SHRU .S1 A_stride, 2, A_stride ;
|
|
|| LDDW .D1T1 *A_ptr_x[A_l2], A_xl2p1:A_xl2p0 ;
|
|
; ============================ PIPE LOOP KERNEL ==============================
|
|
LOOP_Y:
|
|
ADD .S1 A_p2r, A_p3r, A_y_l1_0 ;[25,1]
|
|
|| ADDAH .D2 B_y_h2_0, B_p01r, B_y_h2_0 ;[25,1]
|
|
|| MPYHIR .M1X A_si10, B_yt1, A_p1r ;[15,2]
|
|
|| MPYHIR .M2 B_co10, B_xt1, B_p0r ;[15,2]
|
|
|| PACKH2 .L1 A_yt0, A_xt0, A_yt0xt0 ;[15,2]
|
|
|| PACK2 .L2 B_si10, B_co10, B_si10co10 ;[15,2]
|
|
|| LDDW .D1T2 *A_w2[A_j], B_co30:B_si30 ;[ 5,3]
|
|
|| MV .S2X A_j, B_j ;[ 5,3]
|
|
|
|
[!B_pro]STDW .D2T2 B_y_l2_1:B_y_l2_0, *B_x__[B_l2] ;[26,1]
|
|
|| ADDAH .D1 A_y_l1_1, A_p23c, A_y_l1_1 ;[26,1]
|
|
|| SUB .S2X B_p0c, A_p1c, B_y_h2_1 ;[26,1]
|
|
|| SHR .S1 A_y_h1_0, 1, A_y_h1_0 ;[16,2]
|
|
|| MPYHIR .M2 B_co30, B_xt2, B_p4r ;[16,2]
|
|
|| MPYHIR .M1 A_co20, A_yt0, A_p2c ;[16,2]
|
|
|| PACK2 .L2 B_co30, B_si30, B_co30si30 ;[16,2]
|
|
|| SUB .L1X B_fft_jmp, A_j, A_ifj ;[ 6,3]
|
|
|
|
ADDAH .D2 B_y_h2_1, B_p01c, B_y_h2_1 ;[27,1]
|
|
||[!A_pro]STDW .D1T1 A_y_h1_1:A_y_h1_0, *A_x_1[0] ;[17,2]
|
|
|| DOTPNRSU2.M2 B_yt2xt2, B_co30si30, B_p45c ;[17,2]
|
|
|| MPYHIR .M1 A_si20, A_yt0, A_p3r ;[17,2]
|
|
|| PACK2 .L1 A_co20, A_si20, A_co20si20 ;[17,2]
|
|
|| PACK2 .S2 B_co10, B_si10, B_co10si10 ;[17,2]
|
|
|| SUB .L2X B_xp1, A_xl1p1, B_xl1 ;[ 7,3]
|
|
|| ADD .S1X B_xp1, A_xl1p1, A_xh1 ;[ 7,3]
|
|
|
|
SUB .L2 B_p4c, B_p5c, B_y_l2_1 ;[18,2]
|
|
|| DOTPNRSU2.M2 B_yt1xt1, B_co10si10, B_p01c ;[18,2]
|
|
||[!A_ifj]ADD .S1 A_x, A_fft_jmp, A_x ;[ 8,3]
|
|
|| MVD .M1 A_x, A_x_1 ;[ 8,3]
|
|
|| LDDW .D2T1 *B_w1[B_j], A_co20:A_si20 ;[ 8,3]
|
|
|| LDDW .D1T2 *A_w0[A_j], B_co10:B_si10 ;[ 8,3]
|
|
|| SUB .S2X B_xp0, A_xl1p0, B_xl0 ;[ 8,3]
|
|
|| ADD .L1X B_xp0, A_xl1p0, A_xh0 ;[ 8,3]
|
|
|
|
BDEC .S2 LOOP_Y, B_i ;[29,1]
|
|
||[!B_pro]STDW .D2T2 B_y_h2_1:B_y_h2_0, *B_x__[B_h2] ;[29,1]
|
|
|| ADDAH .D1 A_y_l1_0, A_p23r, A_y_l1_0 ;[29,1]
|
|
|| MPYHIR .M1 A_si20, A_xt0, A_p3c ;[19,2]
|
|
|| DOTPRSU2.M2 B_yt1xt1, B_si10co10, B_p01r ;[19,2]
|
|
|| ADD .S1 A_x, 8, A_x ;[ 9,3]
|
|
|| SUB .L2X B_xh2p0, A_xl2p0, B_xl20 ;[ 9,3]
|
|
|| ADD .L1X B_xh2p0, A_xl2p0, A_xh20 ;[ 9,3]
|
|
|
|
[!B_pro]STDW .D2T1 A_y_l1_1:A_y_l1_0, *B_x__[B_l1] ;[30,1]
|
|
|| MPYHIR .M1 A_co20, A_xt0, A_p2r ;[20,2]
|
|
|| MPYHIR .M2 B_co10, B_yt1, B_p0c ;[20,2]
|
|
|| PACK2 .S1 A_si20, A_co20, A_si20co20 ;[20,2]
|
|
|| ADD .S2 B_xl20, B_xl1, B_yt2 ;[10,3]
|
|
|| ADD .L1 A_xh20, A_xh0, A_y_h1_0 ;[10,3]
|
|
|| SUB .L2X B_xh2p1, A_xl2p1, B_xl21 ;[10,3]
|
|
|| ADD .D1X B_xh2p1, A_xl2p1, A_xh21 ;[10,3]
|
|
|
|
MV .D2X A_x_1, B_x__ ;[21,2]
|
|
|| ADD .S2 B_p4r, B_p5r, B_y_l2_0 ;[21,2]
|
|
|| ADD .L1 A_j, 3, A_j ;[11,3]
|
|
|| MPYHIR .M2 B_co30, B_yt2, B_p4c ;[11,3]
|
|
|| SUB .L2 B_xl0, B_xl21, B_xt2 ;[11,3]
|
|
|| ADD .S1 A_xh21, A_xh1, A_y_h1_1 ;[11,3]
|
|
|| LDDW .D1T1 *A_x[A_l1], A_xl1p1:A_xl1p0 ;[ 1,4]
|
|
|| MPYSU .M1 0, A_pro, A_pro ;
|
|
|
|
ADDAH .D2 B_y_l2_0, B_p45r, B_y_l2_0 ;[22,2]
|
|
|| DOTPNRSU2.M1 A_yt0xt0, A_co20si20, A_p23c ;[22,2]
|
|
||[!A_ifj]ZERO .L1 A_j ;[12,3]
|
|
|| SHR .S1 A_y_h1_1, 1, A_y_h1_1 ;[12,3]
|
|
|| MPYHIR .M2 B_si30, B_yt2, B_p5r ;[12,3]
|
|
|| PACKH2 .S2 B_yt2, B_xt2, B_yt2xt2 ;[12,3]
|
|
|| ADD .L2 B_xl21, B_xl0, B_xt1 ;[12,3]
|
|
|| LDDW .D1T2 *A_x[0], B_xp1:B_xp0 ;[ 2,4]
|
|
|
|
ADDAH .D2 B_y_l2_1, B_p45c, B_y_l2_1 ;[23,2]
|
|
|| SUB .L1 A_p2c, A_p3c, A_y_l1_1 ;[23,2]
|
|
|| DOTPRSU2.M1 A_yt0xt0, A_si20co20, A_p23r ;[23,2]
|
|
|| MPYHIR .M2 B_si30, B_xt2, B_p5c ;[13,3]
|
|
|| MV .S1X B_si10, A_si10 ;[13,3]
|
|
|| PACK2 .L2 B_si30, B_co30, B_si30co30 ;[13,3]
|
|
|| SUB .S2 B_xl1, B_xl20, B_yt1 ;[13,3]
|
|
|| LDDW .D1T2 *A_x[A_h2], B_xh2p1:B_xh2p0 ;[ 3,4]
|
|
|
|
ADD .L2 B_pro, B_pro, B_pro ;[34,1]
|
|
|| ADD .D2X B_p0r, A_p1r, B_y_h2_0 ;[24,2]
|
|
|| DOTPRSU2.M2 B_yt2xt2, B_si30co30, B_p45r ;[14,3]
|
|
|| MPYHIR .M1X A_si10, B_xt1, A_p1c ;[14,3]
|
|
|| PACKH2 .S2 B_yt1, B_xt1, B_yt1xt1 ;[14,3]
|
|
|| SUB .L1 A_xh1, A_xh21, A_yt0 ;[14,3]
|
|
|| SUB .S1 A_xh0, A_xh20, A_xt0 ;[14,3]
|
|
|| LDDW .D1T1 *A_x[A_l2], A_xl2p1:A_xl2p0 ;[ 4,4]
|
|
|
|
; ============================ PIPE LOOP EPILOG ==============================
|
|
ADD .S1 A_p2r, A_p3r, A_y_l1_0 ;
|
|
|| ADDAH .D2 B_y_h2_0, B_p01r, B_y_h2_0 ;[25,4]
|
|
|| CMPGTU .L1 A_stride, A_radix, A_whl ;
|
|
|
|
STDW .D2T2 B_y_l2_1:B_y_l2_0, *B_x__[B_l2] ;[26,4]
|
|
|| ADDAH .D1 A_y_l1_1, A_p23c, A_y_l1_1 ;[26,4]
|
|
|| SUB .S2X B_p0c, A_p1c, B_y_h2_1 ;
|
|
||[A_whl]B .S1 LOOP_WHILE ;} end while
|
|
|
|
ADDAH .D2 B_y_h2_1, B_p01c, B_y_h2_1 ;[27,4]
|
|
|| ADDAH .D1 A_ptr_w, A_tw_offset,A_w0 ;
|
|
|| SHRU .S1 A_stride, 2, A_h2 ;[ 6,0]
|
|
|
|
ADDAH .D1 A_h2, A_h2, A_l2 ;[ 7,0]
|
|
|| MVK .L1 1, A_pro ;
|
|
|| MVK .L2 1, B_pro ;[11,0]
|
|
|
|
STDW .D2T2 B_y_h2_1:B_y_h2_0, *B_x__[B_h2] ;[29,4]
|
|
|| ADDAH .D1 A_y_l1_0, A_p23r, A_y_l1_0 ;[29,4]
|
|
|| ADD .L2X A_w0, 8, B_w1 ;[ 8,0]
|
|
|| MPYSU .M1 6, A_stride, A_fft_jmp ;
|
|
|| SHRU .S1 A_stride, 1, A_l1 ;[10,0]
|
|
|
|
STDW .D2T1 A_y_l1_1:A_y_l1_0, *B_x__[B_l1] ;[30,4]
|
|
|
|
MV .L2X A_l2, B_l2 ;[ 9,0]
|
|
|| SHL .S2 B_pro, 30, B_pro ;[11,0]
|
|
|| LDDW .D1T1 *A_ptr_x[A_l1], A_xl1p1:A_xl1p0 ;
|
|
|
|
; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
|
|
.asg A14, A_radix
|
|
.asg A6, A_ptr_x
|
|
.asg B6, B_ptr_y
|
|
.asg B4, B_n
|
|
.asg A0, A_r2
|
|
.asg A20, A_p_x0
|
|
.asg B8, B_p_x0
|
|
.asg B21, B_p_y0
|
|
.asg B22, B_p_y2
|
|
.asg B23, B_p_y1
|
|
.asg B3, B_p_y3
|
|
.asg B20, B_l1
|
|
.asg B19, B_j0
|
|
.asg A18, A_i
|
|
.asg B9, B_j
|
|
.asg A1, A_pro ;
|
|
; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
|
|
.asg B9, B_j
|
|
.asg A18, A_i
|
|
.asg B19, B_j0
|
|
.asg B20, B_l1
|
|
.asg B21, B_p_y0
|
|
.asg B23, B_p_y1
|
|
.asg B22, B_p_y2
|
|
.asg B3, B_p_y3
|
|
.asg A20, A_p_x0
|
|
.asg B8, B_p_x0
|
|
.asg A0, A_r2
|
|
.asg B25, B_h0
|
|
.asg B7, B_h1
|
|
.asg B7, B_h2
|
|
.asg B5, B_h3
|
|
.asg B16, B_h4
|
|
.asg A7, A_x1
|
|
.asg A6, A_x0
|
|
.asg B29, B_x3
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.asg B28, B_x2
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.asg A5, A_x5
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.asg A4, A_x4
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.asg B5, B_x7
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.asg B4, B_x6
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.asg A21, A_xh0_0
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.asg A3, A_xh1_0
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.asg B24, B_xh0_1
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.asg B26, B_xh1_1
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.asg B24, B_y0
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.asg B25, B_y1
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.asg B6, B_y4
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.asg B7, B_y5
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.asg A16, A_xl0_0
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.asg A19, A_xl1_0
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.asg B18, B_xl0_1
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.asg B17, B_xl1_1
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.asg A16, A_y2
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.asg A17, A_y3
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.asg A8, A_y6
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.asg A9, A_y7
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.asg A22, A_temp
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; ============================ PIPE LOOP PROLOG ==============================
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NORM .L2 B_n, B_l1 ;[ 2,0]
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|| MV .D2 B_ptr_y, B_p_y0 ;[ 2,0]
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|| MVK .L1 1, A_pro ;
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ZERO .L2 B_j ;[ 3,0]
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|| SUB .D1 A_radix, 2, A_r2 ;[ 3,0]
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|| ADD .S2 B_l1, 2, B_l1 ;[ 3,0]
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|| ADDAW .D2 B_p_y0, B_n, B_p_y2 ;[ 3,0]
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MVK .S2 4, B_j0 ;[ 4,0]
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||[!A_r2]NORM .L2 B_n, B_l1 ;[ 4,0]
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|| ADDAH .D2 B_p_y2, B_n, B_p_y3 ;[ 4,0]
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|| SHL .S1 A_pro, 15, A_pro ;
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SHRU .S1X B_n, 2, A_i ;[ 5,0]
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||[!A_r2]MVK .S2 8, B_j0 ;[ 5,0]
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||[!A_r2]ADD .L2 B_l1, 1, B_l1 ;[ 5,0]
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|| ADDAH .D2 B_p_y0, B_n, B_p_y1 ;[ 5,0]
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[!A_r2]ADD .S2 B_p_y2, B_n, B_p_y3 ;[ 6,0]
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||[!A_r2]ADD .L2 B_p_y0, B_n, B_p_y1 ;[ 6,0]
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|| ADD .D2X A_ptr_x, 8, B_p_x0 ;[ 6,0]
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|| MV .L1 A_ptr_x, A_p_x0 ;[ 6,0]
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; ============================ PIPE LOOP KERNEL ==============================
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LOOP_Z:
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[!A_r2]ROTL .M1 A_x4, 0, A_xl0_0 ;[13,1]
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|| SUB .L1X A_xl1_0, B_xl0_1, A_y3 ;[13,1]
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|| ADD .S2X A_xh1_0, B_xh1_1, B_y1 ;[13,1]
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|| BDEC .S1 LOOP_Z, A_i ;[13,1]
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|| ADD .L2 B_j, B_j0, B_j ;[ 1,3]
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|| LDDW .D2T2 *B_p_x0++[2], B_x3:B_x2 ;[ 1,3]
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|| LDDW .D1T1 *A_p_x0++[2], A_x1:A_x0 ;[ 1,3]
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|| DEAL .M2 B_j, B_h0 ;[ 1,3]
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[!A_pro]STDW .D2T2 B_y1:B_y0, *B_p_y0[B_h4] ;[14,1]
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|| MV .S1 A_y3, A_temp ;[14,1]
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|| ADD .L1X A_xl1_0, B_xl0_1, A_y7 ;[14,1]
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|| SUB .L2 B_x2, B_x6, B_xl0_1 ;[ 8,2]
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|| ADD .S2 B_x6, B_x2, B_xh0_1 ;[ 8,2]
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|| ADD .D1 A_x4, A_x0, A_xh0_0 ;[ 8,2]
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||[!A_r2]ROTL .M1 A_x0, 0, A_xh0_0 ;[ 8,2]
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||[!A_r2]ROTL .M2 B_x2, 0, B_xh0_1 ;[ 8,2]
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|
|
|
SUB .L1X A_xl0_0, B_xl1_1, A_y6 ;[15,1]
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|
|| SUB .L2X A_xh1_0, B_xh1_1, B_y5 ;[15,1]
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|
|| ADD .S1 A_x5, A_x1, A_xh1_0 ;[ 9,2]
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||[!A_r2]ROTL .M1 A_x1, 0, A_xh1_0 ;[ 9,2]
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|
||[!A_r2]MV .S2 B_x7, B_xl0_1 ;[ 9,2]
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|
|| SHFL .M2 B_h2, B_h3 ;[ 9,2]
|
|
|| LDDW .D1T1 *A_p_x0++[2], A_x5:A_x4 ;[ 3,3]
|
|
|| LDDW .D2T2 *B_p_x0++[2], B_x7:B_x6 ;[ 3,3]
|
|
|
|
ADD .S1X A_xl0_0, B_xl1_1, A_y2 ;[16,1]
|
|
||[!A_r2]MV .D1 A_y7, A_y3 ;[16,1]
|
|
||[!A_pro]STDW .D2T2 B_y5:B_y4, *B_p_y2[B_h4] ;[16,1]
|
|
|| SUB .L1 A_x1, A_x5, A_xl1_0 ;[10,2]
|
|
||[!A_r2]ROTL .M1 A_x5, 0, A_xl1_0 ;[10,2]
|
|
|| ADD .S2 B_x7, B_x3, B_xh1_1 ;[10,2]
|
|
|| SUB .L2 B_x3, B_x7, B_xl1_1 ;[10,2]
|
|
|| BITR .M2 B_h0, B_h1 ;[ 4,3]
|
|
|
|
[!A_r2]MV .L1 A_temp, A_y7 ;[17,1]
|
|
||[!A_pro]STDW .D2T1 A_y3:A_y2, *B_p_y1[B_h4] ;[17,1]
|
|
|| SUB .D1 A_x0, A_x4, A_xl0_0 ;[11,2]
|
|
|| ADD .L2X A_xh0_0, B_xh0_1, B_y0 ;[11,2]
|
|
|| SUB .S2X A_xh0_0, B_xh0_1, B_y4 ;[11,2]
|
|
||[!A_r2]ROTL .M2 B_x3, 0, B_xh1_1 ;[11,2]
|
|
|
|
[!A_pro]STDW .D2T1 A_y7:A_y6, *B_p_y3[B_h4] ;[18,1]
|
|
|| SHRU .S2 B_h3, B_l1, B_h4 ;[12,2]
|
|
||[!A_r2]MV .L2 B_x6, B_xl1_1 ;[12,2]
|
|
|| ROTL .M2 B_h1, 16, B_h2 ;[ 6,3]
|
|
|| MPYSU .M1 2, A_pro, A_pro ;10000
|
|
|| MV .S1X B_SP, A_SP ; Twin Stack Pointer
|
|
; ============================ PIPE LOOP EPILOG ==============================
|
|
LDW .D1T2 *+A_SP[ 1], B_ret ; Get return address
|
|
|| LDW .D2T1 *+B_SP[ 2], A_csr ; Get CSR's value
|
|
|
|
LDW .D1T2 *+A_SP[ 3], B10 ; Restore B10
|
|
|| LDW .D2T1 *+B_SP[ 4], A10 ; Restore A10
|
|
|
|
LDW .D1T2 *+A_SP[ 5], B11 ; Restore B11
|
|
|| LDW .D2T1 *+B_SP[ 6], A11 ; Restore A11
|
|
|
|
LDW .D1T2 *+A_SP[ 7], B12 ; Restore B12
|
|
|| LDW .D2T1 *+B_SP[ 8], A12 ; Restore A12
|
|
|
|
LDW .D1T2 *+A_SP[ 9], B13 ; Restore B13
|
|
|| LDW .D2T1 *+B_SP[10], A13 ; Restore A13
|
|
|
|
LDW .D1T2 *+A_SP[11], B14 ; Restore B14
|
|
|| LDW .D2T1 *+B_SP[12], A14 ; Restore A14
|
|
|
|
LDW .D2T1 *++B_SP[14],A15 ; Restore A15
|
|
|| RETNOP .S2 B_ret, 4 ; Return to caller
|
|
|
|
MVC .S2X A_csr, CSR ; Restore CSR
|
|
*====== Interruptibility state restored
|
|
;====== Branch Occurs =====
|
|
|
|
*==============================================================================*
|
|
*= End of file: dsp_fft32x32s.asm =*
|
|
*==============================================================================*
|
|
* Copyright (c) 2003 Texas Instruments, Incorporated. *
|
|
* All Rights Reserved. *
|
|
*==============================================================================*
|
|
|