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199 lines
12 KiB
199 lines
12 KiB
;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* DSPLIB DSP Signal Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.6 Sun Sep 29 03:32:27 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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* ========================================================================= *
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* TEXAS INSTRUMENTS, INC. *
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* *
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* NAME *
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* DSP_neg32 *
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* *
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* REVISION DATE *
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* 10-Dec-2001 *
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* *
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* USAGE *
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* This routine is C callable, and may be called using the following *
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* C function prototype: *
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* *
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* void DSP_neg32 *
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* ( *
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* int *x, /* Input data array */ *
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* int *r, /* Output data array */ *
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* short nx /* Number of elements. */ *
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* ); *
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* *
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* DESCRIPTION *
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* This routine negates an array of 32-bit integers, and stores *
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* the result either in a new array, or back to the same array. *
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* *
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* void DSP_neg32 *
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* ( *
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* int *x, /* Input data array */ *
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* int *r, /* Output data array */ *
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* short nx /* Number of elements. */ *
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* ) *
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* { *
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* int i; *
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* *
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* for (i = 0; i < nx; i++) *
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* r[i] = -x[i]; *
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* } *
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* *
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* ASSUMPTIONS *
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* The input must be at least 8 elements long, and a multiple of 4. *
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* *
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* The input and output arrays must not overlap, except in the *
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* special case where the input and output pointers are exactly *
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* equal. *
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* *
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* The x and r arrays must be double-word aligned *
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* *
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* MEMORY NOTE *
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* No memory bank hits will occur. *
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* This kernel is ENDIAN NEUTRAL. *
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* *
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* NOTES *
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* Code is interrupt tolerant but not interruptible. It locks out *
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* interrupts for its entire duration. *
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* *
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* CYCLES *
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* cycles = nx/2 + 19. *
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* nx = 96, cycles = 56 cycles *
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* *
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* CODESIZE *
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* 124 bytes *
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* *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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.sect ".text:_neg32"
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.global _DSP_neg32
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_DSP_neg32:
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* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *
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.asg A4, A_x
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.asg B4, B_r
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.asg A6, A_nx
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.asg B5, B_x
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.asg B19, B_x76
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.asg B18, B_x54
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.asg A19, A_x32
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.asg A18, A_x10
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.asg B9, B_r76
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.asg B8, B_r54
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.asg A17, A_r32
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.asg A16, A_r10
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.asg B0, B_p
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.asg A5, A_r
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.asg A0, A_i
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* ========================================================================= *
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* =========================== PIPE LOOP PROLOG ============================ *
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B .S2 loop
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|| SHR .S1 A_nx, 2, A_i
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|| ADD .L2X A_x, 8, B_x
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LDDW .D1T1 *A_x++[2], A_x32:A_x10 ;[ 1,1]
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|| LDDW .D2T2 *B_x++[2], B_x76:B_x54 ;[ 1,1]
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|| SUB A_i, 2, A_i
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[ A_i]BDEC .S1 loop, A_i ;[ 4,2]
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|| ADD .L1X B_r, 8, A_r
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LDDW .D1T1 *A_x++[2], A_x32:A_x10 ;[ 1,2]
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|| LDDW .D2T2 *B_x++[2], B_x76:B_x54 ;[ 1,2]
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|| MVK 2, B_p
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; ===== 2 prolog stages collapsed
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* =========================== PIPE LOOP KERNEL ============================ *
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loop:
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[ B_p]SUB .L2 B_p, 1, B_p ;[ 8,1]
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||[!B_p]STDW .D2T1 A_r32:A_r10, *B_r++[2] ;[ 8,1]
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||[!B_p]STDW .D1T2 B_r76:B_r54, *A_r++[2] ;[ 8,1]
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||[ A_i]BDEC .S1 loop, A_i ;[ 4,3]
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NEG .S1 A_x10, A_r10 ;[ 7,2]
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|| NEG .L1 A_x32, A_r32 ;[ 7,2]
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|| NEG .L2 B_x54, B_r54 ;[ 7,2]
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|| NEG .S2 B_x76, B_r76 ;[ 7,2]
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|| LDDW .D1T1 *A_x++[2], A_x32:A_x10 ;[ 1,5]
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|| LDDW .D2T2 *B_x++[2], B_x76:B_x54 ;[ 1,5]
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* =========================== PIPE LOOP EPILOG ============================ *
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; ===== 2 epilog stages collapsed
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STDW .D2T1 A_r32:A_r10, *B_r++[2] ;[ 8,4]
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|| STDW .D1T2 B_r76:B_r54, *A_r++[2] ;[ 8,4]
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|| RET B3
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NEG .S1 A_x10, A_r10 ;[ 7,5]
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|| NEG .L1 A_x32, A_r32 ;[ 7,5]
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|| NEG .L2 B_x54, B_r54 ;[ 7,5]
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|| NEG .S2 B_x76, B_r76 ;[ 7,5]
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STDW .D2T1 A_r32:A_r10, *B_r ;[ 8,5]
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|| STDW .D1T2 B_r76:B_r54, *A_r ;[ 8,5]
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NOP 3
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* ========================================================================= *
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* End of file: dsp_neg32.asm *
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* ------------------------------------------------------------------------- *
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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* ========================================================================= *
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