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507 lines
28 KiB
507 lines
28 KiB
;* ======================================================================== *;
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;* TEXAS INSTRUMENTS, INC. *;
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;* *;
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;* IMGLIB DSP Image/Video Processing Library *;
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;* *;
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;* Release: Revision 1.04b *;
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;* CVS Revision: 1.7 Sun Sep 29 07:07:22 2002 (UTC) *;
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;* Snapshot date: 23-Oct-2003 *;
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;* *;
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;* This library contains proprietary intellectual property of Texas *;
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;* Instruments, Inc. The library and its source code are protected by *;
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;* various copyrights, and portions may also be protected by patents or *;
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;* other legal protections. *;
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;* *;
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;* This software is licensed for use with Texas Instruments TMS320 *;
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;* family DSPs. This license was provided to you prior to installing *;
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;* the software. You may review this license by consulting the file *;
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;* TI_license.PDF which accompanies the files in this library. *;
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;* ------------------------------------------------------------------------ *;
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;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
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;* All Rights Reserved. *;
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;* ======================================================================== *;
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;* ======================================================================== *;
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;* Assembler compatibility shim for assembling 4.30 and later code on *;
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;* tools prior to 4.30. *;
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;* ======================================================================== *;
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.if $isdefed(".ASSEMBLER_VERSION")
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.asg .ASSEMBLER_VERSION, $asmver
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.else
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.asg 0, $asmver
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.endif
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.if ($asmver < 430)
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.asg B, CALL ; Function Call
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.asg B, RET ; Return from a Function
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.asg B, CALLRET ; Function call with Call / Ret chaining.
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.if .TMS320C6400
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.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
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.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
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.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
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.endif
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.asg , .asmfunc ; .func equivalent for hand-assembly code
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.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
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.endif
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;* ======================================================================== *;
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;* End of assembler compatibility shim. *;
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;* ======================================================================== *;
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*============================================================================*
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* *
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* TEXAS INSTRUMENTS, INC. *
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* *
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* NAME *
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* Perimeter: Detection of the boundary of a binary image *
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* *
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* REVISION DATE *
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* 21-Aug-2001 *
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* *
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* USAGE *
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* This routine is C callable, and has the following C prototype: *
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* *
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* int IMG_perimeter *
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* ( *
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* const unsigned char *restrict in, /* Input image */ *
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* int cols, /* Width of input */ *
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* unsigned char *restrict out /* Output image */ *
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* ); *
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* *
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* DESCRIPTION *
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* This routine produces the boundary of a binary image. It echoes *
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* the boundary pixels with a value of 0xFF and sets the other pixels *
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* as 0. Detection of the boundary of a binary image is a segmentation *
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* problem and is done by examining spatial locality of the neighboring *
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* pixels. This is done by using the four connectivity algorithm *
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* *
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* pix_up *
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* pix_lft pix_cent pix_rgt *
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* pix_dn *
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* *
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* The output pixel at location pix_cent is echoed as a boundary pixel *
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* if pix_cent is non-zero and any one of its four neighbors is zero *
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* The four neighbors are shown and stand for the foll: *
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* *
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* pix_up: top pixel *
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* pix_lft: left pixel *
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* pix_rgt: right pixel *
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* pix_dn: bottom pixel *
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* *
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* ASSUMPTIONS *
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* input image must be double-word aligned *
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* cols must be a multiple of 16 *
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* *
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* MEMORY NOTE *
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* No bank conflicts are expected for this kernel. *
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* *
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* TECHNIQUES *
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* *
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* Use double word wide loads and bring in pixels along three lines which *
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* we shall call top, mid and bot. Use split compares to compare if pix- *
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* els are greater than or equal to zero. Use the 4 lsb's to find out *
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* the result. Prepare an 8 bit mask using the result of 2 such split *
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* compares. Perform this operation for the top, middle and botton. *
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* Logically invert the result of mid, left shift and right shift and *
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* add the context information by setting the 8 th bit or the 1st bit. *
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* Use xpnd4 and bitc4 to perform expansion and bit count. Store output *
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* pixels as double word. The actual handassembly code is unrolled once *
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* and computes 16 output pixels in 10 cycles *
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* *
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* CYCLES *
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* 10 * cols/16 + 55 *
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* cols = 720, 505 cycles *
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* *
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* CodeSize: 600 bytes *
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* *
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*============================================================================*
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* Copyright (c) 2003 Texas Instruments, Incorporated. *
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* All Rights Reserved. *
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*============================================================================*
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.sect ".text:_perimeter"
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.global _IMG_perimeter
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_IMG_perimeter:
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*================== SYMBOLIC REGISTER ASSIGNMENTS: SETUP ======================*
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.asg B15, B_SP ; Stack pointer, B datapath
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.asg A3, A_SP ; Stack pointer, A datapath
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.asg B0, B_csr ; CSR's value
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.asg B1, B_no_gie ; CSR w/ GIE bit cleared
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.asg A0, A_csr ; Copy of CSR's value
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.asg B3, B_ret ; Return address
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*==============================================================================*
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; Stack frame. 14 words: A10..A15, B10..B14, B3, CSR, pad
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;-
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STW .D2T1 A15, *B_SP--[14] ; Save A15
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|| MV .S1X B_SP, A_SP ; Twin Stack Pointer
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STW .D1T1 A14, *-A_SP[ 2] ; Save A14
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|| STW .D2T2 B14, *+B_SP[11] ; Save B14
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|| MVC .S2 CSR, B_csr ; Capture CSR
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STW .D1T1 A13, *-A_SP[ 4] ; Save A13
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|| STW .D2T2 B13, *+B_SP[ 9] ; Save B13
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|| AND .L2 B_csr, -2, B_no_gie ; Clear GIE
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;-
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STW .D1T1 A12, *-A_SP[ 6] ; Save A12
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|| STW .D2T2 B12, *+B_SP[ 7] ; Save B12
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STW .D1T1 A11, *-A_SP[ 8] ; Save A11
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|| STW .D2T2 B11, *+B_SP[ 5] ; Save B11
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|| MV .L1X B_csr, A_csr ; Partitioning MV
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STW .D1T1 A10, *-A_SP[10] ; Save A10
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|| STW .D2T2 B10, *+B_SP[ 3] ; Save B10
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|| MVC .S2 B_no_gie, CSR ; Dis interrupts
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; ===== Interrupts masked here =====
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;-
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; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
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.asg A4, A_img_in ;
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.asg B4, B_incols ;
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.asg A6, A_img_out ;
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.asg A11, A_top_ptr ;
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.asg A10, A_mid_ptr ;
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.asg A2, A_bot_ptr ;
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.asg B5, B_top_ptr ;
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.asg B6, B_mid_ptr ;
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.asg B16, B_bot_ptr ;
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.asg A19, A_bot_zero ;
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.asg B19, B_bot_zero ;
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.asg A20, A_k_16 ;
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.asg B20, B_k_16 ;
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.asg A21, A_FF ;
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.asg B21, B_FF ;
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.asg B1, B_lt0 ;
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.asg A3, A_sum ;
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.asg A5, A_optr ;
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.asg B17, B_optr ;
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.asg B2, B_pd ;
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.asg A16, A_byte_ptr ;
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.asg A22, A_mid_rt_const ;
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.asg B22, B_mid_lf_const ;
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.asg A23, A_mid_lf_const ;
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.asg B23, B_mid_rt_const ;
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.asg B18, B_i ;
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; ============================================================================
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MVK .S1 080h, A_mid_rt_const ;[ 1,0]
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|| STW .D1T1 A_csr, *-A_SP[12] ; Save CSR
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|| STW .D2T2 B_ret, *+B_SP[ 1] ; return address
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MV .L1 A_img_out, A_optr ;[ 2,0]
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MV .D2X A_mid_rt_const, B_mid_rt_const ;[ 3,0]
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|| MVK .S1 16, A_k_16 ;[ 3,0]
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SHRU .S2 B_incols, 4, B_i ;[ 4,0]
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|| ADD .L2X A_optr, 8, B_optr ;[ 4,0]
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|| ADD .D1X A_img_in, B_incols, A_bot_ptr ;[ 4,0]
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MVK .L2 01h, B_mid_lf_const ;[ 5,0]
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|| MV .D2X A_k_16, B_k_16 ;[ 5,0]
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|| ADD .S1 A_img_in, 0, A_mid_ptr ;[ 5,0]
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ADD .D2X A_bot_ptr, 8, B_bot_ptr ;[ 6,0]
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|| SUB .L1X A_img_in, B_incols, A_top_ptr ;[ 6,0]
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MV .S1X B_mid_lf_const, A_mid_lf_const ;[ 7,0]
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|| ADD .D1 A_img_in, 16, A_byte_ptr ;[ 7,0]
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|| ZERO .D2 B_lt0 ;[ 7,0]
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|| ADD .L2X A_mid_ptr, 8, B_mid_ptr ;[ 7,0]
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|| MVK .S2 3, B_pd
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ZERO .L2 B_bot_zero ;[ 8,0]
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|| ZERO .D1 A_bot_zero ;[ 8,0]
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|| ADD .D2X A_top_ptr, 8, B_top_ptr ;[ 8,0]
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;==== Branch occurs
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; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
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.asg A11, A_top_ptr
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.asg A10, A_mid_ptr
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.asg A2, A_bot_ptr
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.asg B5, B_top_ptr
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.asg B6, B_mid_ptr
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.asg B16, B_bot_ptr
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.asg A19, A_bot_zero
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.asg B19, B_bot_zero
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.asg A20, A_k_16
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.asg B20, B_k_16
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.asg A21, A_FF
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.asg B21, B_FF
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.asg B1, B_lt0
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.asg A3, A_sum
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.asg A5, A_optr
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.asg B17, B_optr
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.asg B2, B_pd
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.asg A22, A_mid_rt_const
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.asg B22, B_mid_lf_const
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.asg A23, A_mid_lf_const
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.asg B23, B_mid_rt_const
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.asg A16, A_byte_ptr
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.asg B18, B_i
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.asg A27, A_top_word1
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.asg A26, A_top_word0
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.asg A31, A_mid_word1
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.asg A30, A_mid_word0
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.asg A29, A_bot_word1
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.asg A28, A_bot_word0
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.asg B27, B_top_word3
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.asg B26, B_top_word2
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.asg B31, B_mid_word3
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.asg B30, B_mid_word2
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.asg B29, B_bot_word3
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.asg B28, B_bot_word2
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.asg A17, A_mid_word0c
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.asg A9, A_mid_word1c
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.asg B12, B_mid_word2c
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.asg B29, B_mid_word3c
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.asg A25, A_midval00
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.asg A7, A_midval01
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.asg B7, B_midval02
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.asg B8, B_midval03
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.asg A8, A_midval01_s
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.asg B3, B_midval03_s
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.asg A18, A_midval_w0
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.asg B3, B_midval_w1
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.asg A26, A_upval00
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.asg A24, A_upval01
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.asg B26, B_upval02
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.asg B9, B_upval03
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.asg A24, A_upval01_s
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.asg B25, B_upval03_s
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.asg A8, A_upval_w0
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.asg B10, B_upval_w1
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.asg A8, A_botval00
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.asg A7, A_botval01
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.asg B28, B_botval02
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.asg B8, B_botval03
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.asg A24, A_botval01_s
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.asg B9, B_botval03_s
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.asg A27, A_botval_w0
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.asg B27, B_botval_w1
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.asg A30, A_midval_k0
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.asg B8, B_midval_k1
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.asg A9, A_mid_rt_val0
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.asg B8, B_mid_rt_val1
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.asg A27, A_mid_lt_val0
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.asg B7, B_mid_lt_val1
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.asg B0, B_rt0
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.asg A1, A_lt1
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.asg A0, A_rt1
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.asg A12, A_updnval0
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.asg A7, A_rgtlft0
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.asg A7, A_udrl0
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.asg A25, A_udrlm0
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.asg B11, B_updnval1
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.asg B7, B_rgtlft1
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.asg B7, B_udrl1
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.asg B8, B_udrlm1
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.asg A30, A_count0
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.asg B7, B_count1
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.asg A25, A_count
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.asg A24, A_pixel0
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.asg A7, A_udrlm_s
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.asg A25, A_pixel1
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.asg B24, B_pixel2
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.asg B14, B_udrl_r
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.asg B25, B_pixel3
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; ============================================================================
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; START:
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; ============================ PIPE LOOP PROLOG ==============================
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; PROLOG:
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LDDW .D2T2 *B_top_ptr++[2], B_top_word3:B_top_word2 ;[ 1,1]
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|| LDDW .D1T1 *A_bot_ptr++[2], A_bot_word1:A_bot_word0 ;[ 1,1]
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|| ZERO .L1 A_sum ;[ 8,0]
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|| MVK .S2 0FFh, B_FF ;[ 8,0]
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|| MVK .S1 0FFh, A_FF ;[ 8,0]
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LDDW .D2T2 *B_bot_ptr++[2], B_bot_word3:B_bot_word2 ;[ 2,1]
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NOP 3 ;
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CMPEQ4 .S2 B_top_word3, B_bot_zero, B_upval03 ;[ 6,1]
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MPY .M2 B_upval03, B_k_16, B_upval03_s ;[ 7,1]
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; ============================ PIPE LOOP KERNEL ==============================
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LOOP:
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OR .D1 A_mid_rt_val0, A_mid_lt_val0, A_rgtlft0 ;
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|| OR .L2 B_mid_rt_val1, B_mid_lt_val1, B_rgtlft1 ;
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|| AND .D2 B_mid_word2, B_FF, B_rt0 ;
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|| ADD .L1 A_botval01_s, A_botval00, A_botval_w0 ;
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|| SHRU .S1 A_mid_word1, 24, A_lt1 ;
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|| CMPGTU4 .S2 B_mid_word3, B_bot_zero, B_midval03 ;
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|| MPY .M1 A_midval01, A_k_16, A_midval01_s ;
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OR .L1 A_updnval0, A_rgtlft0, A_udrl0 ;
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|| OR .L2 B_updnval1, B_rgtlft1, B_udrl1 ;
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||[ B_pd]SUB .D2 B_pd, 1, B_pd ;
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|| CMPEQ4 .S1 A_top_word0, A_bot_zero, A_upval00 ;
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|| MPY .M2 B_midval03, B_k_16, B_midval03_s ;
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|| LDDW .D1T1 *A_top_ptr++[2], A_top_word1:A_top_word0 ;
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|| CMPEQ4 .S2 B_bot_word3, B_bot_zero, B_botval03 ;
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AND .L1 A_udrl0, A_midval_w0, A_udrlm0 ;
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|| AND .L2 B_udrl1, B_midval_w1, B_udrlm1 ;
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|| MVD .M1 A_mid_word0, A_mid_word0c ;
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|| CMPGTU4 .S2 B_mid_word2, B_bot_zero, B_midval02 ;
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|| ADD .S1 A_midval01_s, A_midval00, A_midval_w0 ;
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|| MPY .M2 B_botval03, B_k_16, B_botval03_s ;
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|| LDDW .D2T2 *B_top_ptr++[2], B_top_word3:B_top_word2 ;
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|| LDDW .D1T1 *A_bot_ptr++[2], A_bot_word1:A_bot_word0 ;
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SHRU .S1 A_udrlm0, 4, A_udrlm_s ;
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|| XPND4 .M1 A_udrlm0, A_pixel0 ;
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|| XPND4 .M2 B_udrlm1, B_pixel2 ;
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|| SHRU .S2 B_udrlm1, 4, B_udrl_r ;
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|| ADD .L2 B_midval03_s, B_midval02, B_midval_w1 ;
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|| NOT .L1 A_midval_w0, A_midval_k0 ;
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|| LDDW .D1T1 *A_mid_ptr++[2], A_mid_word1:A_mid_word0 ;
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|| LDDW .D2T2 *B_bot_ptr++[2], B_bot_word3:B_bot_word2 ;
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BDEC .S2 LOOP, B_i ;
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|| XPND4 .M1 A_udrlm_s, A_pixel1 ;
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|| BITC4 .M2 B_udrlm1, B_count1 ;
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|| ADD .L1 A_upval01_s, A_upval00, A_upval_w0 ;
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|| OR .D2 B_upval_w1, B_botval_w1, B_updnval1 ;
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|| NOT .L2 B_midval_w1, B_midval_k1 ;
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|| AND .D1 A_midval_k0, A_FF, A_midval_k0 ;
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|| CMPEQ4 .S1 A_bot_word1, A_bot_zero, A_botval01 ;
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BITC4 .M1 A_udrlm0, A_count0 ;
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|| AND .D1 A_pixel0, A_mid_word0c, A_pixel0 ;
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|| XPND4 .M2 B_udrl_r, B_pixel3 ;
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|| OR .L1 A_upval_w0, A_botval_w0, A_updnval0 ;
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|| AND .L2 B_midval_k1, B_FF, B_midval_k1 ;
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|| CMPEQ4 .S1 A_bot_word0, A_bot_zero, A_botval00 ;
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|| CMPEQ4 .S2 B_top_word2, B_bot_zero, B_upval02 ;
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|| LDDW .D2T2 *B_mid_ptr++[2], B_mid_word3:B_mid_word2 ;
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AND .L1 A_pixel1, A_mid_word1c, A_pixel1 ;
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|| AND .L2 B_pixel2, B_mid_word2c, B_pixel2 ;
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|| SHRU .S1 A_midval_k0, 1, A_mid_rt_val0 ;
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|| MPY .M2 B_midval_k1, 2, B_mid_lt_val1 ;
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|| MPY .M1 A_midval_k0, 2, A_mid_lt_val0 ;
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|| LDBU .D1T1 *A_byte_ptr++[16], A_rt1 ;
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|| ADD .D2 B_upval03_s, B_upval02, B_upval_w1 ;
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|| CMPEQ4 .S2 B_bot_word2, B_bot_zero, B_botval02 ;
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[!B_pd]STNDW .D1T1 A_pixel1:A_pixel0, *A_optr++[2] ;
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|| ADD .L1X A_count0, B_count1, A_count ;
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|| AND .D2 B_pixel3, B_mid_word3c, B_pixel3 ;
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|| MVD .M2 B_mid_word2, B_mid_word2c ;
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|| MVD .M1 A_mid_word1, A_mid_word1c ;
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|| ADD .L2 B_botval03_s, B_botval02, B_botval_w1 ;
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|| CMPEQ4 .S1 A_top_word1, A_bot_zero, A_upval01 ;
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|| CMPEQ4 .S2 B_top_word3, B_bot_zero, B_upval03 ;
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[!B_pd]ADD .L1 A_sum, A_count, A_sum ;
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||[!B_pd]STNDW .D2T2 B_pixel3:B_pixel2, *B_optr++[2] ;
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|| SHRU .S2 B_midval_k1, 1, B_mid_rt_val1 ;
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|| AND .D1 A_mid_lt_val0, A_FF, A_mid_lt_val0 ;
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|| AND .L2 B_mid_lt_val1, B_FF, B_mid_lt_val1 ;
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|| CMPGTU4 .S1 A_mid_word0, A_bot_zero, A_midval00 ;
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|| MPY .M1 A_botval01, A_k_16, A_botval01_s ;
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|| MPY .M2 B_upval03, B_k_16, B_upval03_s ;
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MVD .M2 B_mid_word3, B_mid_word3c ;
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||[!B_rt0]ADD .D1 A_mid_rt_val0, A_mid_rt_const, A_mid_rt_val0 ;
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||[!A_rt1]ADD .L2 B_mid_rt_val1, B_mid_rt_const, B_mid_rt_val1 ;
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||[!B_lt0]ADD .L1 A_mid_lt_val0, A_mid_lf_const, A_mid_lt_val0 ;
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||[!A_lt1]ADD .D2 B_mid_lt_val1, B_mid_lf_const, B_mid_lt_val1 ;
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|| SHRU .S2 B_mid_word3, 24, B_lt0 ;
|
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|| MPY .M1 A_upval01, A_k_16, A_upval01_s ;
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|| CMPGTU4 .S1 A_mid_word1, A_bot_zero, A_midval01 ;
|
|
|
|
; ============================ PIPE LOOP EPILOG ==============================
|
|
; EPILOG:
|
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|
|
; ============================================================================
|
|
; END:
|
|
|
|
|
|
; ====================== SYMBOLIC REGISTER ASSIGNMENTS =======================
|
|
.asg A19, A_bot_zero ;
|
|
.asg A6, A_img_out ;
|
|
.asg B4, B_incols ;
|
|
.asg A3, A_sum ;
|
|
.asg A4, A_ret_val ;
|
|
.asg A0, A_p0
|
|
.asg A5, A_offset
|
|
.asg A0, A_p1
|
|
.asg B15, B_SP ; Stack pointer, B datapath
|
|
.asg A15, A_SP ; Stack pointer, A datapath
|
|
.asg A0, A_csr ; CSR value to restore
|
|
.asg B3, B_ret ; Return address
|
|
.asg B0, B_p1
|
|
.asg B14, B_udrl_r
|
|
;============================================================================
|
|
|
|
LDBU .D1T1 *A_img_out, A_p0 ;
|
|
|| SUB .S1X B_incols, 1, A_offset ;
|
|
|
|
SHRU .S2 B_udrl_r, 3, B_p1
|
|
|| MV .S1X B_SP, A_SP ; Twin Stack Pointer
|
|
|
|
LDW .D1T2 *+A_SP[ 1], B_ret ; Get return address
|
|
|| LDW .D2T1 *+B_SP[ 2], A_csr ; Get CSR's value
|
|
|
|
LDW .D1T2 *+A_SP[ 3], B10 ; Restore B10
|
|
|| LDW .D2T1 *+B_SP[ 4], A10 ; Restore A10
|
|
|
|
LDW .D1T2 *+A_SP[ 5], B11 ; Restore B11
|
|
|| LDW .D2T1 *+B_SP[ 6], A11 ; Restore A11
|
|
|
|
|
|
[ A_p0]SUB .L1 A_sum, 1, A_sum ;
|
|
|| LDW .D1T2 *+A_SP[ 7], B12 ; Restore B12
|
|
|| LDW .D2T1 *+B_SP[ 8], A12 ; Restore A12
|
|
|
|
[ B_p1]SUB .S1 A_sum, 1, A_sum ;
|
|
|| LDW .D1T2 *+A_SP[ 9], B13 ; Restore B13
|
|
|| LDW .D2T1 *+B_SP[10], A13 ; Restore A13
|
|
|
|
;==== Branch occurs ;
|
|
|
|
|
|
*================== SYMBOLIC REGISTER ASSIGNMENTS: SETUP ======================*
|
|
.asg B15, B_SP ; Stack pointer, B datapath
|
|
.asg A15, A_SP ; Stack pointer, A datapath
|
|
.asg A0, A_csr ; CSR value to restore
|
|
.asg B3, B_ret ; Return address
|
|
*==============================================================================*
|
|
|
|
LDW .D1T2 *+A_SP[11], B14 ; Restore B14
|
|
|| LDW .D2T1 *+B_SP[12], A14 ; Restore A14
|
|
|| RET .S2 B_ret ; Return to caller
|
|
|
|
MVC .S2X A_csr, CSR ; Restore CSR
|
|
|| LDW .D2T1 *++B_SP[14],A15 ; Restore A15
|
|
*====== Interruptibility state restored here ==================================*
|
|
|
|
STB .D1T1 A_bot_zero, *+A_img_out[A_offset] ;
|
|
|
|
MV .L1 A_sum, A_ret_val ;
|
|
|| STB .D1T1 A_bot_zero, *A_img_out ;
|
|
|
|
NOP 2
|
|
;====== Branch Occurs =====
|
|
|
|
*==============================================================================*
|
|
*= End of file: img_perimeter.asm =*
|
|
*==============================================================================*
|
|
* Copyright (c) 2003 Texas Instruments, Incorporated. *
|
|
* All Rights Reserved. *
|
|
*==============================================================================*
|
|
|