You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
242 lines
14 KiB
242 lines
14 KiB
;* ======================================================================== *;
|
|
;* TEXAS INSTRUMENTS, INC. *;
|
|
;* *;
|
|
;* DSPLIB DSP Signal Processing Library *;
|
|
;* *;
|
|
;* Release: Revision 1.04b *;
|
|
;* CVS Revision: 1.9 Thu Oct 3 11:08:07 2002 (UTC) *;
|
|
;* Snapshot date: 23-Oct-2003 *;
|
|
;* *;
|
|
;* This library contains proprietary intellectual property of Texas *;
|
|
;* Instruments, Inc. The library and its source code are protected by *;
|
|
;* various copyrights, and portions may also be protected by patents or *;
|
|
;* other legal protections. *;
|
|
;* *;
|
|
;* This software is licensed for use with Texas Instruments TMS320 *;
|
|
;* family DSPs. This license was provided to you prior to installing *;
|
|
;* the software. You may review this license by consulting the file *;
|
|
;* TI_license.PDF which accompanies the files in this library. *;
|
|
;* ------------------------------------------------------------------------ *;
|
|
;* Copyright (C) 2003 Texas Instruments, Incorporated. *;
|
|
;* All Rights Reserved. *;
|
|
;* ======================================================================== *;
|
|
|
|
|
|
;* ======================================================================== *;
|
|
;* Assembler compatibility shim for assembling 4.30 and later code on *;
|
|
;* tools prior to 4.30. *;
|
|
;* ======================================================================== *;
|
|
|
|
.if $isdefed(".ASSEMBLER_VERSION")
|
|
.asg .ASSEMBLER_VERSION, $asmver
|
|
.else
|
|
.asg 0, $asmver
|
|
.endif
|
|
|
|
.if ($asmver < 430)
|
|
|
|
.asg B, CALL ; Function Call
|
|
.asg B, RET ; Return from a Function
|
|
.asg B, CALLRET ; Function call with Call / Ret chaining.
|
|
|
|
.if .TMS320C6400
|
|
.asg BNOP, CALLNOP ; C64x BNOP as a Fn. Call
|
|
.asg BNOP, RETNOP ; C64x BNOP as a Fn. Return
|
|
.asg BNOP, CRNOP ; C64x Fn call w/, Call/Ret chaining via BNOP.
|
|
.endif
|
|
|
|
.asg , .asmfunc ; .func equivalent for hand-assembly code
|
|
.asg , .endasmfunc ; .endfunc equivalent for hand-assembly code
|
|
|
|
.endif
|
|
|
|
;* ======================================================================== *;
|
|
;* End of assembler compatibility shim. *;
|
|
;* ======================================================================== *;
|
|
|
|
|
|
* ========================================================================= *
|
|
* *
|
|
* TEXAS INSTRUMENTS, INC. *
|
|
* *
|
|
* NAME *
|
|
* DSP_fltoq15 *
|
|
* *
|
|
* REVISION DATE *
|
|
* 03-Oct-2002 *
|
|
* *
|
|
* USAGE *
|
|
* This routine is C-callable and can be called as: *
|
|
* *
|
|
* void DSP_fltoq15(float x[], short r[], short nx) *
|
|
* *
|
|
* x[nx] : Pointer to values of type float *
|
|
* r[nx] : Contains Q15 values from x[nx] *
|
|
* nx : Number of elements in arrays *
|
|
* *
|
|
* DESCRIPTION *
|
|
* Convert the IEEE floating point numbers stored in vector x[] into *
|
|
* Q.15 format numbers stored in vector r[]. Results are truncated *
|
|
* towards zero. Values that exceed the size limit will be saturated *
|
|
* to 0x7fff if value is positive and 0x8000 if value is negative. *
|
|
* All values too small to be correctly represented will be truncated *
|
|
* to 0. *
|
|
* *
|
|
* The 16-bit Q.15 format is defined as follows: *
|
|
* *
|
|
* 1 11111 *
|
|
* 5 432109876543210 *
|
|
* S.XXXXXXXXXXXXXXX *
|
|
* *
|
|
* range: 1.000000000000000 = -1.0 <-> -32768 *
|
|
* 0.111111111111111 = 0.999969482421875 <-> 32767 *
|
|
* *
|
|
* IEEE floating point format is defined as follows: *
|
|
* *
|
|
* 31 30....23 22.....0 *
|
|
* S EXPONENT MANTISSA *
|
|
* *
|
|
* The value is obtained as: (-1)^S * 1.MANTISSA * 2^(EXPONENT-127) *
|
|
* *
|
|
* C CODE *
|
|
* void DSP_fltoq15(float x[], short r[], short nx) *
|
|
* { *
|
|
* int i, a; *
|
|
* *
|
|
* for(i = 0; i < nx; i++) *
|
|
* { *
|
|
* a = 32768 * x[i]; *
|
|
* *
|
|
* // saturate to 16-bit // *
|
|
* if (a>32767) a = 32767; *
|
|
* if (a<-32768) a = -32768; *
|
|
* *
|
|
* r[i] = (short) a; *
|
|
* } *
|
|
* } *
|
|
* *
|
|
* ASSUMPTIONS *
|
|
* 1. nx >= 2 *
|
|
* 2. nx is a multiple of 2 *
|
|
* *
|
|
* NOTES *
|
|
* This code is interrupt-tolerant but not interruptible. *
|
|
* This implementation is ENDIAN NEUTRAL. *
|
|
* *
|
|
* TECHNIQUE *
|
|
* Loop is unrolled twice. *
|
|
* *
|
|
* CYCLES *
|
|
* 3 * nx/2 + 17 *
|
|
* *
|
|
* This cycle count includes 6 cycles of function call overhead. *
|
|
* The exact overhead will vary depending on the compiler options *
|
|
* used. *
|
|
* *
|
|
* CODESIZE *
|
|
* 168 bytes *
|
|
* *
|
|
* ------------------------------------------------------------------------- *
|
|
* Copyright (c) 2003 Texas Instruments, Incorporated. *
|
|
* All Rights Reserved. *
|
|
* ========================================================================= *
|
|
|
|
|
|
.sect ".text:_fltoq15"
|
|
.global _DSP_fltoq15
|
|
_DSP_fltoq15:
|
|
* ===================== SYMBOLIC REGISTER ASSIGNMENTS ===================== *
|
|
.asg A4, A_x_ptr
|
|
.asg B4, B_r_ptr
|
|
.asg A6, A_nx
|
|
.asg A8, A_bit23
|
|
.asg B16, B_offset
|
|
.asg B9, B_ma_mask
|
|
.asg A7, A_c31
|
|
.asg B8, B_bit23
|
|
.asg A5, A_offset
|
|
.asg A3, A_ma_mask
|
|
.asg B5, B_c31
|
|
.asg B7, B_fl_val_1
|
|
.asg B6, B_fl_val
|
|
.asg B7, B_mant
|
|
.asg B7, B_exp
|
|
.asg B0, B_sign
|
|
.asg B19, B_manti
|
|
.asg B18, B_shift
|
|
.asg B17, B_fract
|
|
.asg A18, A_fl_val_1
|
|
.asg A17, A_mant_1
|
|
.asg A16, A_exp_1
|
|
.asg A0, A_sign_1
|
|
.asg A17, A_manti_1
|
|
.asg A16, A_shift_1
|
|
.asg A9, A_fract_1
|
|
.asg A18, A_fracts_1
|
|
.asg B1, B_p
|
|
.asg A1, A_i
|
|
* ========================================================================= *
|
|
|
|
* =========================== PIPE LOOP PROLOG ============================ *
|
|
LDNDW .D1T2 *A_x_ptr++, B_fl_val_1:B_fl_val ;[ 1,1]
|
|
|| MVKL .S1 0x7FFFFF, A_ma_mask ;setup
|
|
|| ZERO .L1 A_bit23 ;setup
|
|
|| MVK .S2 135, B_offset ;setup
|
|
|
|
SET .S1 A_bit23, 23, 23, A_bit23 ;setup
|
|
|| MVK .S2 31, B_c31 ;setup
|
|
|
|
B .S2 loop ;[12,1]
|
|
|| MVKH .S1 0x7FFFFF, A_ma_mask ;setup
|
|
|
|
LDNDW .D1T2 *A_x_ptr++, B_fl_val_1:B_fl_val ;[ 1,2]
|
|
|| SHR .S1 A_nx, 1, A_i ;setup
|
|
|| MV .L1X B_c31, A_c31 ;setup
|
|
|| MV .L2X A_bit23, B_bit23 ;setup
|
|
|
|
MVK .S2 3, B_p ;setup
|
|
|| MV .L2X A_ma_mask, B_ma_mask ;setup
|
|
|| MV .L1X B_offset, A_offset ;setup
|
|
|| SUB A_i, 1, A_i
|
|
|
|
* =========================== PIPE LOOP KERNEL ============================ *
|
|
loop:
|
|
[!B_p]STW .D2T1 A_fracts_1, *B_r_ptr++ ;[15,1]
|
|
||[ A_i]BDEC .S1 loop, A_i ;[12,2]
|
|
||[ A_sign_1]NEG.L1 A_fract_1, A_fract_1 ;[12,2]
|
|
||[ B_sign]NEG .L2 B_fract, B_fract ;[12,2]
|
|
|| MV .D1X B_fl_val_1, A_fl_val_1 ;[ 6,4]
|
|
|| EXTU .S2 B_fl_val, 1, 24, B_exp ;[ 6,4]
|
|
|
|
SSHVR .M1 A_manti_1, A_shift_1, A_fract_1 ;[10,3]
|
|
|| SSHVR .M2 B_manti, B_shift, B_fract ;[10,3]
|
|
|| EXTU .S1 A_fl_val_1, 1, 24, A_exp_1 ;[ 7,4]
|
|
|| AND .L1 A_fl_val_1, A_ma_mask, A_mant_1 ;[ 7,4]
|
|
|| SUB .D2 B_offset, B_exp, B_shift ;[ 7,4]
|
|
|| AND .S2 B_fl_val, B_ma_mask, B_mant ;[ 7,4]
|
|
||[ A_i]LDNDW .D1T2 *A_x_ptr++, B_fl_val_1:B_fl_val ;[ 1,6]
|
|
||[ B_p]SUB .L2 B_p, 1, B_p ;prolog coll
|
|
|
|
SPACK2 .S1X A_fract_1, B_fract, A_fracts_1 ;[14,2]
|
|
|| SUB .L1 A_offset, A_exp_1, A_shift_1 ;[ 8,4]
|
|
|| ADD .D1 A_mant_1, A_bit23, A_manti_1 ;[ 8,4]
|
|
|| SSHVR .M1 A_fl_val_1, A_c31, A_sign_1 ;[ 8,4]
|
|
|| ADD .D2 B_mant, B_bit23, B_manti ;[ 8,4]
|
|
|| SSHVR .M2 B_fl_val, B_c31, B_sign ;[ 8,4]
|
|
|
|
* =========================== PIPE LOOP EPILOG ============================ *
|
|
[!B_p] STW .D2T1 A_fracts_1, *B_r_ptr++ ;[15,5]
|
|
||[ A_sign_1]NEG.L1 A_fract_1, A_fract_1 ;[12,6]
|
|
||[ B_sign]NEG .L2 B_fract, B_fract ;[12,6]
|
|
|| RETNOP .S2 B3, 3
|
|
|
|
SPACK2 .S1X A_fract_1, B_fract, A_fracts_1 ;[14,6]
|
|
|
|
STW .D2T1 A_fracts_1, *B_r_ptr ;[15,6]
|
|
|
|
* ========================================================================= *
|
|
* End of file: dsp_fltoq15.asm *
|
|
* ------------------------------------------------------------------------- *
|
|
* Copyright (c) 2003 Texas Instruments, Incorporated. *
|
|
* All Rights Reserved. *
|
|
* ========================================================================= *
|
|
|