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new hyplnk func, and hyplnk intr

master
qshi 6 years ago
parent
7707d25961
commit
455030657d
25 changed files with 779 additions and 1205 deletions
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  1. 179
      packages/vsky/libdsp/driver/hyplink.c
  2. 45
      packages/vsky/libdsp/driver/power_ctrl.c
  3. 267
      packages/vsky/libdsp/hyplnk/hyplnk_device.c
  4. 280
      packages/vsky/libdsp/hyplnk/hyplnk_device.h
  5. 168
      packages/vsky/libdsp/hyplnk/hyplnk_func.c
  6. 23
      packages/vsky/libdsp/hyplnk/hyplnk_func.h
  7. 34
      packages/vsky/libdsp/hyplnk/hyplnk_intr.c
  8. 6
      packages/vsky/libdsp/hyplnk/hyplnk_intr.h
  9. 3
      packages/vsky/libdsp/inc/board.h
  10. 2
      packages/vsky/libdsp/inc/power_ctrl.h
  11. 13
      packages/vsky/libdsp/srio/srio_func.c
  12. 13
      samples/hyperlink/.ccsproject
  13. 147
      samples/hyperlink/.cproject
  14. 96
      samples/hyperlink/.project
  15. 179
      samples/hyperlink/hyplink.c
  16. 258
      samples/hyperlink/hyplink.h
  17. 137
      samples/hyperlink/main.c
  18. 39
      samples/hyperlink/test.cmd
  19. 1
      samples/srio/.cproject
  20. 5
      samples/srio/.project
  21. 5
      samples/srio/src/board.c
  22. 74
      samples/srio/src/hyplnk.c
  23. 4
      samples/srio/src/main.c
  24. 2
      samples/srio/src/net.c
  25. 4
      samples/srio/srio.cfg

179
packages/vsky/libdsp/driver/hyplink.c
View File

@ -1,179 +0,0 @@
/*
* hyplink_init.c
*/
#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_bootcfgAux.h>
#include <ti/csl/cslr_vusr.h>
#include "hyplink.h"
#include "board.h"
#define CFGRX_DEFAULT 0x0046c485
#define CFGTX_DEFAULT 0x001c8f85
#define gpHyperLinkRegs ((CSL_VusrRegs *)CSL_MCM_CONFIG_REGS)
#define gpBootCfgRegs ((CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS)
static int get_rate(unsigned int speed)
{
int rate = 0;
switch (speed) {
case 1250000:
rate = 0x3; // 11b (one data sample is taken every 2 pll output);
break;
case 3125000:
rate = 0x2; // 10b (one data sample is taken every 1 pll output);
break;
case 6250000:
rate = 0x1; // 01b (two data sample is taken every 1 pll output);
break;
case 12500000:
rate = 0x0; // 00b (four data sample is taken every 1 pll output);
break;
default:
break;
}
return (rate);
}
static void get_regval(uint32_t ref,uint32_t speed, int *pllm, int *vo)
{
switch (ref) {
case 156250: {
switch(speed) {
case 1250000:
*pllm = 0x3C; // 0100 0000 (16x --> 2.5G PLL out clock)
*vo = 0;
break;
default:
*pllm = 0x50; // 0101 0000 (20x --> 3.125 PLL out clock)
*vo = 0;
break;
}
} break;
case 250000: {
switch(speed) {
case 1250000:
*pllm = 0x28; // 0010 1000 (10x --> 2.5G PLL out clock)
*vo = 0;
break;
default:
*pllm = 0x50; // 0011 0010 (12.5x --> 3.125 PLL out clock)
*vo = 0;
break;
}
} break;
case 312500: {
switch(speed) {
case 1250000:
*pllm = 0x20; // 0010 0000 (8x --> 2.5G PLL out clock)
*vo = 0;
break;
default:
*pllm = 0x28; // 0010 1000 (10x --> 3.125 PLL out clock)
*vo = 0;
break;
}
} break;
default:
break;
}
}
void hyperlink_addr_map(HyperLink_Address_Map * addr_map)
{
int i;
gpHyperLinkRegs->TX_SEL_CTL =
(addr_map->tx_addr_mask<<CSL_VUSR_TX_SEL_CTL_TXIGNMSK_SHIFT)
|(addr_map->tx_priv_id_ovl<<CSL_VUSR_TX_SEL_CTL_TXPRIVIDOVL_SHIFT);
gpHyperLinkRegs->RX_SEL_CTL =
(addr_map->rx_seg_sel<<CSL_VUSR_RX_SEL_CTL_RXSEGSEL_SHIFT)
|(addr_map->rx_priv_id_sel<<CSL_VUSR_RX_SEL_CTL_RXPRIVIDSEL_SHIFT);
for(i= 0; i< 16; i++)
{
gpHyperLinkRegs->RX_PRIV_IDX= i;
gpHyperLinkRegs->RX_PRIV_VAL= addr_map->rx_priv_id_map[i];
}
for(i= 0; i< 64; i++)
{
gpHyperLinkRegs->RX_SEG_IDX= i;
gpHyperLinkRegs->RX_SEG_VAL=
addr_map->rx_addr_segs[i].Seg_Base_Addr
|addr_map->rx_addr_segs[i].Seg_Length;
}
}
static void __hp_serdesc_init()
{
volatile uint16_t pllcfg;
volatile uint32_t cfgrx,cfgtx;
unsigned int speed, clk;
int rate, pllm = 0, vo = 0;
CSL_BootCfgUnlockKicker();
speed = hyperlink_speed() / 1000;
clk = hyperlink_input_clock() / 1000;
rate = get_rate(speed);
get_regval(clk, speed, &pllm, &vo);
pllcfg = (1<<0)|(vo <<9)|((Uint16)(pllm << 1));
cfgrx = CFGRX_DEFAULT | (rate << 4);
cfgtx = CFGTX_DEFAULT | (rate << 4);
CSL_BootCfgSetVUSRConfigPLL(pllcfg);
CSL_BootCfgSetVUSRRxConfig (0, cfgrx);
CSL_BootCfgSetVUSRRxConfig (1, cfgrx);
CSL_BootCfgSetVUSRRxConfig (2, cfgrx);
CSL_BootCfgSetVUSRRxConfig (3, cfgrx);
CSL_BootCfgSetVUSRTxConfig (0, cfgtx);
CSL_BootCfgSetVUSRTxConfig (1, cfgtx);
CSL_BootCfgSetVUSRTxConfig (2, cfgtx);
CSL_BootCfgSetVUSRTxConfig (3, cfgtx);
CSL_BootCfgLockKicker();
}
void hyperlink_init(HyperLink_Config * hyperLink_cfg)
{
gpHyperLinkRegs->PWR =
(7<<CSL_VUSR_PWR_H2L_SHIFT)
|(7<<CSL_VUSR_PWR_L2H_SHIFT)
|(1<<CSL_VUSR_PWR_PWC_SHIFT)
|(1<<CSL_VUSR_PWR_QUADLANE_SHIFT)
|(0<<CSL_VUSR_PWR_ZEROLANE_SHIFT)
|(0<<CSL_VUSR_PWR_SINGLELANE_SHIFT);
/* enable operation */
gpHyperLinkRegs->CTL &= ~(CSL_VUSR_CTL_SERIAL_STOP_MASK);
hyperlink_addr_map(&hyperLink_cfg->address_map);
/*tell all receivers to ignore close to the first 3uS of data at beginning of training sequence*/
gpHyperLinkRegs->SERDES_CTL_STS1= 0xFFFF0000;
__hp_serdesc_init();
while ((gpBootCfgRegs->STS_VUSR & 0x00000001) != 0x00000001)
;
/*---------wait for link status OK-------------*/
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_SERIAL_HALT_MASK);
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_PLL_UNLOCK_MASK);
while(0==(gpHyperLinkRegs->STS&CSL_VUSR_STS_LINK_MASK));
while(0==(gpHyperLinkRegs->LINK_STS&CSL_VUSR_LINK_STS_RX_ONE_ID_MASK));
/*after initialization, change the delay to default value to improve performance*/
}
void hyperlink_write(void * restrict dst,void * restrict src,uint32_t count)
{
memcpy(dst, src, count);
}

45
packages/vsky/libdsp/driver/power_ctrl.c
View File

@ -6,6 +6,29 @@
*/
#include "ckdef.h"
static void __enable_psc_module(Uint32 pwrDmnNum, Uint32 moduleNum)
{
if (CSL_PSC_getPowerDomainState(pwrDmnNum) != PSC_PDSTATE_ON) {
/* Set Power domain to ON */
CSL_PSC_enablePowerDomain (pwrDmnNum);
/* Start the state transition */
CSL_PSC_startStateTransition (pwrDmnNum);
/* Wait until the state transition process is completed. */
while (!CSL_PSC_isStateTransitionDone (pwrDmnNum));
}
/* Enable the clocks too */
CSL_PSC_setModuleNextState (moduleNum, PSC_MODSTATE_ENABLE);
/* Start the state transition */
CSL_PSC_startStateTransition (pwrDmnNum);
/* Wait until the state transition process is completed. */
while (!CSL_PSC_isStateTransitionDone (pwrDmnNum));
}
void power_up_domains(void )
{
/* PASS power domain is turned OFF by default. It needs to be turned on before doing any
@ -44,6 +67,8 @@ void power_up_domains(void )
void power_up_srio(void )
{
__enable_psc_module(CSL_PSC_PD_SRIO, CSL_PSC_LPSC_SRIO);
#if 0
/* Set SRIO Power domain to ON */
CSL_PSC_enablePowerDomain (CSL_PSC_PD_SRIO);
@ -55,4 +80,24 @@ void power_up_srio(void )
/* Wait until the state transition process is completed. */
while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_SRIO));
#endif //
}
void power_up_hyplnk(void )
{
__enable_psc_module(CSL_PSC_PD_HYPERBRIDGE, CSL_PSC_LPSC_HYPERBRIDGE);
#if 0
/* Set HYPLNK Power domain to ON */
CSL_PSC_enablePowerDomain (CSL_PSC_PD_HYPERBRIDGE);
/* Enable the clocks too for HYPLNK */
CSL_PSC_setModuleNextState (CSL_PSC_LPSC_HYPERBRIDGE, PSC_MODSTATE_ENABLE);
/* Start the state transition */
CSL_PSC_startStateTransition (CSL_PSC_PD_HYPERBRIDGE);
/* Wait until the state transition process is completed. */
while (!CSL_PSC_isStateTransitionDone (CSL_PSC_PD_HYPERBRIDGE));
#endif //
}

267
packages/vsky/libdsp/hyplnk/hyplnk_device.c
View File

@ -0,0 +1,267 @@
/*
* hyplink_init.c
*/
#include <stdint.h>
#include <stdio.h>
#include <ti/csl/csl_bootcfgAux.h>
#include <ti/csl/cslr_vusr.h>
#include "power_ctrl.h"
#include "tsc.h"
#include "board.h"
#include "hyplnk_device.h"
#define CFGRX_DEFAULT 0x0046c485
#define CFGTX_DEFAULT 0x001c8f85
#define gpHyperLinkRegs ((CSL_VusrRegs *)CSL_MCM_CONFIG_REGS)
#define gpBootCfgRegs ((CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS)
static void __hyplnk_serdesc_init(eHYPLNKREFCLK ref_clock, eHYPLNKLANERATE lane_speed)
{
volatile uint32_t pllcfg;
volatile uint32_t cfgrx,cfgtx;
uint32_t rate, pllm, vo;
/* get pllm val. */
switch(ref_clock) {
case HYPLNK_REF_CLOCK_156P25MHZ:
switch(lane_speed) {
case HYPLNK_LANE_SPEED_1P250GPS:
pllm = 0x3C; // 0100 0000 (16x --> 2.5G PLL out clock)
break;
default:
pllm = 0x50; // 0101 0000 (20x --> 3.125 PLL out clock)
break;
}
break;
case HYPLNK_REF_CLOCK_250P00MHZ:
switch(lane_speed) {
case HYPLNK_LANE_SPEED_1P250GPS:
pllm = 0x28; // 0010 1000 (10x --> 2.5G PLL out clock)
break;
default:
pllm = 0x50; // 0011 0010 (12.5x --> 3.125 PLL out clock)
break;
}
break;
case HYPLNK_REF_CLOCK_312P50MHZ:
switch(lane_speed) {
case HYPLNK_LANE_SPEED_1P250GPS:
pllm = 0x20; // 0010 0000 (8x --> 2.5G PLL out clock)
break;
default:
pllm = 0x28; // 0010 1000 (10x --> 3.125 PLL out clock)
break;
}
break;
}
/* because pll out clock is 2.5G or 3.125 is always more than 2.17G, so vo is 0*/
vo = 0;
/* get rate val. */
switch (lane_speed) {
case HYPLNK_LANE_SPEED_1P250GPS:
rate = 0x3; // 11b (one data sample is taken every 2 pll output);
break;
case HYPLNK_LANE_SPEED_3P125GPS:
rate = 0x2; // 10b (one data sample is taken every 1 pll output);
break;
case HYPLNK_LANE_SPEED_6P25GPS:
rate = 0x1; // 01b (two data sample is taken every 1 pll output);
break;
case HYPLNK_LANE_SPEED_12P5GPS:
rate = 0x0; // 00b (four data sample is taken every 1 pll output);
break;
default:
break;
}
CSL_BootCfgUnlockKicker();
/*
* SerDes PLL Configuration Register Field, other bits is reserved.
* [9]: pll Volt Range
* [8-1]: MPY
* [0]: enable pll
*/
pllcfg = (vo << 9) | ((pllm * 4) << 1) | (1 << 0);
/*
* SerDes rx/tx Configuration Register Field, other bits is reserved.
* [5-4]: rate bits
*/
cfgrx = CFGRX_DEFAULT | (rate << 4);
cfgtx = CFGTX_DEFAULT | (rate << 4);
CSL_BootCfgSetVUSRConfigPLL(pllcfg);
CSL_BootCfgSetVUSRRxConfig (0, cfgrx);
CSL_BootCfgSetVUSRRxConfig (1, cfgrx);
CSL_BootCfgSetVUSRRxConfig (2, cfgrx);
CSL_BootCfgSetVUSRRxConfig (3, cfgrx);
CSL_BootCfgSetVUSRTxConfig (0, cfgtx);
CSL_BootCfgSetVUSRTxConfig (1, cfgtx);
CSL_BootCfgSetVUSRTxConfig (2, cfgtx);
CSL_BootCfgSetVUSRTxConfig (3, cfgtx);
CSL_BootCfgLockKicker();
}
static inline void __wait_hyplnk_pll_lock()
{
while ((gpBootCfgRegs->STS_VUSR & 0x00000001) != 0x00000001);
}
int hyplnk_dev_init(eHYPLNKREFCLK ref_clock, eHYPLNKLANERATE lane_speed)
{
/* enable hyplnk power and clock domain. */
power_up_hyplnk();
/* wait for power module up complete. */
tsc_delay(2000);
/* force 4 lanes always. */
gpHyperLinkRegs->PWR =
(7<<CSL_VUSR_PWR_H2L_SHIFT)
|(7<<CSL_VUSR_PWR_L2H_SHIFT)
|(1<<CSL_VUSR_PWR_PWC_SHIFT)
|(1<<CSL_VUSR_PWR_QUADLANE_SHIFT)
|(0<<CSL_VUSR_PWR_ZEROLANE_SHIFT)
|(0<<CSL_VUSR_PWR_SINGLELANE_SHIFT);
/* enable operation */
gpHyperLinkRegs->CTL &= ~(CSL_VUSR_CTL_SERIAL_STOP_MASK);
/* tell all receivers to ignore close to the first 3uS of data at beginning of training sequence*/
gpHyperLinkRegs->SERDES_CTL_STS1= 0xFFFF0000;
/* hyplnk serdes init. */
__hyplnk_serdesc_init(ref_clock, lane_speed);
__wait_hyplnk_pll_lock();
/*---------wait for link status OK-------------*/
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_SERIAL_HALT_MASK);
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_PLL_UNLOCK_MASK);
while(0==(gpHyperLinkRegs->STS&CSL_VUSR_STS_LINK_MASK));
while(0==(gpHyperLinkRegs->LINK_STS&CSL_VUSR_LINK_STS_RX_ONE_ID_MASK));
return 0;
}
int hyplnk_dev_addr_map(Hpk_Address_Map_s *addr_map)
{
int i;
CSL_VusrRegs *gp_Remote_regs = (CSL_VusrRegs *)&gpHyperLinkRegs->REM_REGS;
gpHyperLinkRegs->TX_SEL_CTL =
(addr_map->tx_addr_mask<<CSL_VUSR_TX_SEL_CTL_TXIGNMSK_SHIFT)
|(addr_map->tx_priv_id_ovl<<CSL_VUSR_TX_SEL_CTL_TXPRIVIDOVL_SHIFT);
gp_Remote_regs->RX_SEL_CTL =
(addr_map->rx_seg_sel<<CSL_VUSR_RX_SEL_CTL_RXSEGSEL_SHIFT)
|(addr_map->rx_priv_id_sel<<CSL_VUSR_RX_SEL_CTL_RXPRIVIDSEL_SHIFT);
for (i= 0; i< 16; i++) {
gp_Remote_regs->RX_PRIV_IDX= i;
gp_Remote_regs->RX_PRIV_VAL= addr_map->rx_priv_id_map[i];
}
for (i= 0; i< 64; i++) {
gp_Remote_regs->RX_SEG_IDX= i;
gp_Remote_regs->RX_SEG_VAL=
addr_map->rx_addr_segs[i].Seg_Base_Addr
| addr_map->rx_addr_segs[i].Seg_Length;
}
return 0;
}
void hyplnk_dev_intr_init(hpk_intr_cfg_s * int_cfg)
{
int i;
gpHyperLinkRegs->CTL = gpHyperLinkRegs->CTL
|(int_cfg->int_local<<CSL_VUSR_CTL_INTLOCAL_SHIFT)
|(int_cfg->sts_int_enable<<CSL_VUSR_CTL_INTENABLE_SHIFT)
|(int_cfg->sts_int_vec<<CSL_VUSR_CTL_INTVEC_SHIFT)
|(int_cfg->int2cfg<<CSL_VUSR_CTL_INT2CFG_SHIFT);
for(i=0; i<64; i++)
{
gpHyperLinkRegs->INT_CTL_IDX = i;
gpHyperLinkRegs->INT_CTL_VAL=
(int_cfg->int_event_cntl[i].Int_en<<CSL_VUSR_INT_CTL_VAL_INTEN_SHIFT)
|(int_cfg->int_event_cntl[i].Int_type<<CSL_VUSR_INT_CTL_VAL_INTTYPE_SHIFT)
|(int_cfg->int_event_cntl[i].Int_pol<<CSL_VUSR_INT_CTL_VAL_INTPOL_SHIFT)
|(int_cfg->int_event_cntl[i].si_en<<CSL_VUSR_INT_CTL_VAL_SIEN_SHIFT)
|(int_cfg->int_event_cntl[i].mps<<CSL_VUSR_INT_CTL_VAL_MPS_SHIFT)
|(int_cfg->int_event_cntl[i].vector<<CSL_VUSR_INT_CTL_VAL_VECTOR_SHIFT);
}
for(i=0; i<NUM_MPS; i++)
{
gpHyperLinkRegs->INT_PTR_IDX = i;
gpHyperLinkRegs->INT_PTR_VAL= int_cfg->int_set_register_pointer[i];
}
//clear any pending interrupt
gpHyperLinkRegs->INT_CLR= 0xFFFFFFFF;
}
void hyplnk_dev_trigger_intr(uint8_t hw_vector)
{
/*manually trigger the hardware event, which will generate
interrupt packet to remote side*/
gpHyperLinkRegs->SW_INT = hw_vector;
}
void hyplnk_dev_intr_handle(void )
{
Uint32 intVector;
/*read the HyperLink interrupt vector*/
intVector= gpHyperLinkRegs->INT_PRI_VEC;
while(0==(intVector&CSL_VUSR_INT_PRI_VEC_NOINTPEND_MASK))
{
if(0==intVector)//HyperLink error is routed to vector 0 for this test.
{
//print status
//printf("hyplnk error !!!\n");
//print_HyperLink_status();
/*disable all portal or remote register operation
This bit should be set before iloop or reset bits are changed.*/
gpHyperLinkRegs->CTL |= CSL_VUSR_CTL_SERIAL_STOP_MASK;
/*Wait until no Remote Pending Request*/
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_RPEND_MASK);
/*Reset*/
//gpHyperLinkRegs->CTL |= CSL_VUSR_CTL_RESET_MASK;
//clear error status
gpHyperLinkRegs->STS |= CSL_VUSR_STS_LERROR_MASK
|CSL_VUSR_STS_RERROR_MASK;
/*release from Reset*/
//gpHyperLinkRegs->CTL &= ~(CSL_VUSR_CTL_RESET_MASK);
/*enable operation*/
gpHyperLinkRegs->CTL &= ~(CSL_VUSR_CTL_SERIAL_STOP_MASK);
}
/*write back to clear that interrupt*/
gpHyperLinkRegs->INT_PRI_VEC= intVector;
gpHyperLinkRegs->INT_CLR= (1<<intVector);
/*read the HyperLink interrupt vector*/
intVector= gpHyperLinkRegs->INT_PRI_VEC;
}
}

280
packages/vsky/libdsp/inc/hyplink.h → packages/vsky/libdsp/hyplnk/hyplnk_device.h
View File

@ -11,40 +11,45 @@
#include <stdint.h>
#include <stdio.h>
#define NUM_MPS 8 /*Number of supported Micro Processor*/
#define HYPERLINK_INPUT_CLCK_156p25 156.25
#define HYPERLINK_INPUT_CLCK_250 250
#define HYPERLINK_INPUT_CLCK_312p5 312.5
#define HYPERLINK_SPEED_1p25 1.25
#define HYPERLINK_SPEED_3p125 3.125
#define HYPERLINK_SPEED_6p25 6.25
#define HYPERLINK_SPEED_12p5 12.5
#define NUM_MPS 8 /*Number of supported Micro Processor*/
/* hyplnk ref clock define */
typedef enum {
HYPLNK_REF_CLOCK_156P25MHZ = 0, /* 156.25Mhz for HYPLNK */
HYPLNK_REF_CLOCK_250P00MHZ, /* 250.00Mhz for HYPLNK */
HYPLNK_REF_CLOCK_312P50MHZ /* 312.50Mhz for HYPLNK */
}eHYPLNKREFCLK;
/* hyplnk lanes speed define */
typedef enum {
HYPLNK_LANE_SPEED_1P250GPS = 0, /* rate of 1.25 Gbps for HYPLNK lanes */
HYPLNK_LANE_SPEED_3P125GPS, /* rate of 3.125 Gbps for HYPLNK lanes */
HYPLNK_LANE_SPEED_6P25GPS, /* rate of 6.25 Gbps for HYPLNK lanes */
HYPLNK_LANE_SPEED_12P5GPS /* rate of 12.5 Gbps for HYPLNK lanes */
}eHYPLNKLANERATE;
/*select which bits of the RxAddress are used to select which
Segment/Length array element value to Add/Check to the Address signal.*/
typedef enum
{
typedef enum {
RX_SEG_SEL_0, /*always use 0 as index to lookup segment/length table*/
RX_SEG_SEL_ADDR_22_17,
RX_SEG_SEL_ADDR_23_18,
RX_SEG_SEL_ADDR_24_19,
RX_SEG_SEL_ADDR_25_20,
RX_SEG_SEL_ADDR_26_21,
RX_SEG_SEL_ADDR_27_22,
RX_SEG_SEL_ADDR_28_23,
RX_SEG_SEL_ADDR_29_24,
RX_SEG_SEL_ADDR_30_25,
RX_SEG_SEL_ADDR_31_26,
RX_SEG_SEL_ADDR_31_27,
RX_SEG_SEL_ADDR_31_28,
RX_SEG_SEL_ADDR_31_29,
RX_SEG_SEL_ADDR_31_30,
RX_SEG_SEL_ADDR_31
}HyperLink_RxSegSel;
typedef enum
{
RX_SEG_SEL_ADDR_22_17, /* 1 */
RX_SEG_SEL_ADDR_23_18, /* 2 */
RX_SEG_SEL_ADDR_24_19, /* 3 */
RX_SEG_SEL_ADDR_25_20, /* 4 */
RX_SEG_SEL_ADDR_26_21, /* 5 */
RX_SEG_SEL_ADDR_27_22, /* 6 */
RX_SEG_SEL_ADDR_28_23, /* 7 */
RX_SEG_SEL_ADDR_29_24, /* 8 */
RX_SEG_SEL_ADDR_30_25, /* 9 */
RX_SEG_SEL_ADDR_31_26, /* 10 */
RX_SEG_SEL_ADDR_31_27, /* 11 */
RX_SEG_SEL_ADDR_31_28, /* 12 */
RX_SEG_SEL_ADDR_31_29, /* 13 */
RX_SEG_SEL_ADDR_31_30, /* 14 */
RX_SEG_SEL_ADDR_31 /* 15 */
} eHPK_RxSegSel;
typedef enum {
RX_SEG_LEN_0x0_0000_0002,
RX_SEG_LEN_0x0_0000_0004,
RX_SEG_LEN_0x0_0000_0008,
@ -77,139 +82,136 @@ typedef enum
RX_SEG_LEN_0x0_4000_0000,
RX_SEG_LEN_0x0_8000_0000,
RX_SEG_LEN_0x1_0000_0000
}HyperLink_RxSegLen;
}eHPK_RxSegLen;
typedef struct{
uint32_t Seg_Base_Addr; /*low 16 bits must be 0*/
HyperLink_RxSegLen Seg_Length; /*must be power of 2, 0~0x100000000*/
}HyperLink_Rx_Address_Segment;
eHPK_RxSegLen Seg_Length; /*must be power of 2, 0~0x100000000*/
}Hpk_Rx_Address_Segment_s;
/*select which bits of the RxAddress are used to select which PrivID
array element value to drive to the PrivID signal.*/
typedef enum
{
RX_PRIVID_0, /*always use 0 as privID*/
RX_PRIVID_SEL_ADDR_20_17,
RX_PRIVID_SEL_ADDR_21_18,
RX_PRIVID_SEL_ADDR_22_19,
RX_PRIVID_SEL_ADDR_23_20,
RX_PRIVID_SEL_ADDR_24_21,
RX_PRIVID_SEL_ADDR_25_22,
RX_PRIVID_SEL_ADDR_26_23,
RX_PRIVID_SEL_ADDR_27_24,
RX_PRIVID_SEL_ADDR_28_25,
RX_PRIVID_SEL_ADDR_29_26,
RX_PRIVID_SEL_ADDR_30_27,
RX_PRIVID_SEL_ADDR_31_28,
RX_PRIVID_SEL_ADDR_31_29,
RX_PRIVID_SEL_ADDR_31_30,
RX_PRIVID_SEL_ADDR_31
}HyperLink_RxPrivIdSel;
typedef enum {
RX_PRIVID_0 = 0, /*always use 0 as privID*/
RX_PRIVID_SEL_ADDR_20_17, /* 1 */
RX_PRIVID_SEL_ADDR_21_18, /* 2 */
RX_PRIVID_SEL_ADDR_22_19, /* 3 */
RX_PRIVID_SEL_ADDR_23_20, /* 4 */
RX_PRIVID_SEL_ADDR_24_21, /* 5 */
RX_PRIVID_SEL_ADDR_25_22, /* 6 */
RX_PRIVID_SEL_ADDR_26_23, /* 7 */
RX_PRIVID_SEL_ADDR_27_24, /* 8 */
RX_PRIVID_SEL_ADDR_28_25, /* 9 */
RX_PRIVID_SEL_ADDR_29_26, /* 10 */
RX_PRIVID_SEL_ADDR_30_27, /* 11 */
RX_PRIVID_SEL_ADDR_31_28, /* 12 */
RX_PRIVID_SEL_ADDR_31_29, /* 13 */
RX_PRIVID_SEL_ADDR_31_30, /* 14 */
RX_PRIVID_SEL_ADDR_31 /* 15 */
}eHPK_RxPrivIdSel;
/*Specifies where the PrivID is placed in the outgoing TxAddress.*/
typedef enum
{
TX_PRIVID_NO_OVERLAY,
TX_PRIVID_OVL_ADDR_20_17,
TX_PRIVID_OVL_ADDR_21_18,
TX_PRIVID_OVL_ADDR_22_19,
TX_PRIVID_OVL_ADDR_23_20,
TX_PRIVID_OVL_ADDR_24_21,
TX_PRIVID_OVL_ADDR_25_22,
TX_PRIVID_OVL_ADDR_26_23,
TX_PRIVID_OVL_ADDR_27_24,
TX_PRIVID_OVL_ADDR_28_25,
TX_PRIVID_OVL_ADDR_29_26,
TX_PRIVID_OVL_ADDR_30_27,
TX_PRIVID_OVL_ADDR_31_28,
TX_PRIVID_OVL_ADDR_31_29,
TX_PRIVID_OVL_ADDR_31_30,
TX_PRIVID_OVL_ADDR_31
}HyperLink_TxPrivIdOvl;
typedef enum {
TX_PRIVID_NO_OVERLAY = 0,
TX_PRIVID_OVL_ADDR_20_17, /* 1 */
TX_PRIVID_OVL_ADDR_21_18, /* 2 */
TX_PRIVID_OVL_ADDR_22_19, /* 3 */
TX_PRIVID_OVL_ADDR_23_20, /* 4 */
TX_PRIVID_OVL_ADDR_24_21, /* 5 */
TX_PRIVID_OVL_ADDR_25_22, /* 6 */
TX_PRIVID_OVL_ADDR_26_23, /* 7 */
TX_PRIVID_OVL_ADDR_27_24, /* 8 */
TX_PRIVID_OVL_ADDR_28_25, /* 9 */
TX_PRIVID_OVL_ADDR_29_26, /* 10 */
TX_PRIVID_OVL_ADDR_30_27, /* 11 */
TX_PRIVID_OVL_ADDR_31_28, /* 12 */
TX_PRIVID_OVL_ADDR_31_29, /* 13 */
TX_PRIVID_OVL_ADDR_31_30, /* 14 */
TX_PRIVID_OVL_ADDR_31 /* 15 */
}eHPK_TxPrivIdOvl;
/*create the mask that is logically anded to the incoming address to create
the address sent to the remote.*/
typedef enum
{
TX_ADDR_MASK_0x0001FFFF,
TX_ADDR_MASK_0x0003FFFF,
TX_ADDR_MASK_0x0007FFFF,
TX_ADDR_MASK_0x000FFFFF,
TX_ADDR_MASK_0x001FFFFF,
TX_ADDR_MASK_0x003FFFFF,
TX_ADDR_MASK_0x007FFFFF,
TX_ADDR_MASK_0x00FFFFFF,
TX_ADDR_MASK_0x01FFFFFF,
TX_ADDR_MASK_0x03FFFFFF,
TX_ADDR_MASK_0x07FFFFFF,
TX_ADDR_MASK_0x0FFFFFFF,
TX_ADDR_MASK_0x1FFFFFFF,
TX_ADDR_MASK_0x3FFFFFFF,
TX_ADDR_MASK_0x7FFFFFFF,
TX_ADDR_MASK_0xFFFFFFFF
}HyperLink_TxAddrMask;
typedef struct{
typedef enum {
TX_ADDR_MASK_0x0001FFFF = 0,
TX_ADDR_MASK_0x0003FFFF, /* 1 */
TX_ADDR_MASK_0x0007FFFF, /* 2 */
TX_ADDR_MASK_0x000FFFFF, /* 3 */
TX_ADDR_MASK_0x001FFFFF, /* 4 */
TX_ADDR_MASK_0x003FFFFF, /* 5 */
TX_ADDR_MASK_0x007FFFFF, /* 6 */
TX_ADDR_MASK_0x00FFFFFF, /* 7 */
TX_ADDR_MASK_0x01FFFFFF, /* 8 */
TX_ADDR_MASK_0x03FFFFFF, /* 9 */
TX_ADDR_MASK_0x07FFFFFF, /* 10 */
TX_ADDR_MASK_0x0FFFFFFF, /* 11 */
TX_ADDR_MASK_0x1FFFFFFF, /* 12 */
TX_ADDR_MASK_0x3FFFFFFF, /* 13 */
TX_ADDR_MASK_0x7FFFFFFF, /* 14 */
TX_ADDR_MASK_0xFFFFFFFF /* 15 */
}eHPK_TxAddrMask;
typedef struct {
/*create the mask that is logically anded to the incoming address to create
the address sent to the remote.*/
HyperLink_TxAddrMask tx_addr_mask;
eHPK_TxAddrMask tx_addr_mask;
/*Specifies where the PrivID is placed in the outgoing TxAddress.*/
HyperLink_TxPrivIdOvl tx_priv_id_ovl;
eHPK_TxPrivIdOvl tx_priv_id_ovl;
/*The rxsegsel value is used to select which bits of the RxAddress
are used to select which Segment/Length array element value to
Add/Check to the Address signal.*/
HyperLink_RxSegSel rx_seg_sel;
eHPK_RxSegSel rx_seg_sel;
HyperLink_Rx_Address_Segment rx_addr_segs[64];
Hpk_Rx_Address_Segment_s rx_addr_segs[64];
/*The rxprividsel value is used to select which bits of the
RxAddress are used to select which PrivID array element
value to drive to the PrivID signal.*/
HyperLink_RxPrivIdSel rx_priv_id_sel;
eHPK_RxPrivIdSel rx_priv_id_sel;
uint8_t rx_priv_id_map[16];
}HyperLink_Address_Map;
}Hpk_Address_Map_s;
typedef struct{
/*Interrupt Enable. When set, this bit indicates that interrupts detected
on the Hyperlink_int_i[icidx] pin should be should be forwarded to the
/*Interrupt Enable. When set, this bit indicates that interrupts detected
on the Hyperlink_int_i[icidx] pin should be should be forwarded to the
below mps:vector interrupt vector.*/
uint8_t Int_en;
/*Interrupt Type. When set, this bit indicates that the
/*Interrupt Type. When set, this bit indicates that the
Hyperlink_int_i[icidx] interrupt is pulsed. When clear, this bit
indicates that Hyperlink_int_i[icidx] is level sensitive.*/
uint8_t Int_type;
/*Interrupt Polarity When set, this bit indicates that the
/*Interrupt Polarity When set, this bit indicates that the
Hyperlink_int_i[icidx)] interrupt is active low. When clear, this
bit indicates that Hyperlink_int_i[icidx] is active high*/
uint8_t Int_pol;
uint8_t Int_pol;
/*Software Interrupt Enable indicate if this interrupt can be issued
/*Software Interrupt Enable indicate if this interrupt can be issued
via software writing to the Generate Soft Interrupt
Value register for this SoftInt[icidx].*/
uint8_t si_en;
uint8_t si_en;
uint8_t mps; /*MicroProcessor Select*/
/*When the local device has int2Local =1, this field indicates which bit
of interrupt pending register to set. When the local device has
int2local =0, this field is transferred to the remote device, which is
used to indicate which bit of the interrupt pending register to set in
/*When the local device has int2Local =1, this field indicates which bit
of interrupt pending register to set. When the local device has
int2local =0, this field is transferred to the remote device, which is
used to indicate which bit of the interrupt pending register to set in
the remote device. */
uint8_t vector;
}HyperLink_int_event_control;
uint8_t vector;
}hpk_int_event_ctl_s;
typedef struct{
/*Interrupt Local. This bit determines whether interrupts are posted in
the Interrupt Status/Clear Register or forwarded via the serial interface.
/*Interrupt Local. This bit determines whether interrupts are posted in
the Interrupt Status/Clear Register or forwarded via the serial interface.
When set, interrupts are posted in the Interrupt Status/Clear Register and
the Hyperlink_intpls_o and Hyperlink_intlvl_o pins are asserted.
When clear, interrupts are forwarded out the serial interface to the remote
the Hyperlink_intpls_o and Hyperlink_intlvl_o pins are asserted.
When clear, interrupts are forwarded out the serial interface to the remote
device.*/
uint8_t int_local;
@ -217,39 +219,29 @@ typedef struct{
be posted to the Interrupt Pending/Set Register*/
uint8_t sts_int_enable;
/*Interrupt Vector. This field indicates which bit in the Interrupt
/*Interrupt Vector. This field indicates which bit in the Interrupt
Pending/Set Register is set for HyperLink module status interrupts.*/
uint8_t sts_int_vec;
uint8_t sts_int_vec;
/*The Interrupt pending register can be set by the remote
device through the interrupt packet, when the int2cfg is set to 1.
/*The Interrupt pending register can be set by the remote
device through the interrupt packet, when the int2cfg is set to 1.
When int2cfg is clear, the interrupt status is extracted from the
received interrupt packet and written to the register indicated by
the Interrupt Pointer Register for the particular micro processor
received interrupt packet and written to the register indicated by
the Interrupt Pointer Register for the particular micro processor
select (MPS) value.*/
uint8_t int2cfg;
uint8_t int2cfg;
HyperLink_int_event_control int_event_cntl[64];
hpk_int_event_ctl_s int_event_cntl[64];
/*The Interrupt Pointer Registers typically map to microprocessor
interrupt controller set registers which get set to a one to interrupt
/*The Interrupt Pointer Registers typically map to microprocessor
interrupt controller set registers which get set to a one to interrupt
that processor.*/
uint8_t int_set_register_pointer[NUM_MPS];
}HyperLink_Interrupt_Cfg;
typedef enum
{
HyperLink_LOOPBACK_DISABLE = 0,
HyperLink_LOOPBACK
}HyperLink_Loopback_Mode;
typedef struct {
HyperLink_Address_Map address_map;
HyperLink_Interrupt_Cfg interrupt_cfg;
HyperLink_Loopback_Mode loopback_mode;
//SerdesSetup_4links serdes_cfg;
} HyperLink_Config;
void hyperlink_write(void * restrict dst, void * restrict src,uint32_t count);
void hyperlink_init(HyperLink_Config * hyperLink_cfg);
uint32_t int_set_register_pointer[NUM_MPS];
}hpk_intr_cfg_s;
int hyplnk_dev_init(eHYPLNKREFCLK ref_clock, eHYPLNKLANERATE lane_speed);
int hyplnk_dev_addr_map(Hpk_Address_Map_s *addr_map);
void hyplnk_dev_intr_init(hpk_intr_cfg_s * int_cfg);
void hyplnk_dev_trigger_intr(uint8_t hw_vector);
void hyplnk_dev_intr_handle(void );
#endif /* HYPLINK_INIT_H_ */

168
packages/vsky/libdsp/hyplnk/hyplnk_func.c
View File

@ -0,0 +1,168 @@
#include <stdio.h>
#include <string.h>
#include "board.h"
#include "hyplnk_device.h"
#include "hyplnk_func.h"
#include "hyplnk_intr.h"
#define hpk_debug printf
#define HYPLNK_LANES_SPEED_DEFAULT HYPLNK_LANE_SPEED_3P125GPS
#define HW_EVENT_FOR_INT_CKDZ 0
struct hyplnk_intr_usr_cfg {
void *arg;
void (*intr_handle)(void *arg);
};
static struct hyplnk_intr_usr_cfg g_hyplnk_intr_usr_cfg;
static eHPK_RxSegLen __hyplnk_seg_len_type(unsigned int seg_len)
{
eHPK_RxSegLen type = RX_SEG_LEN_0x0_0000_0002;
while(seg_len > 2) {
seg_len /=2;
type++;
}
return type;
}
static void __hyplnk_intr_isr(void *arg)
{
struct hyplnk_intr_usr_cfg *intr_cfg = (struct hyplnk_intr_usr_cfg *)arg;
hyplnk_dev_intr_handle();
if (intr_cfg && intr_cfg->intr_handle)
intr_cfg->intr_handle(intr_cfg->arg);
}
int hyplnk_init(void *arg, void (*intr_handle)(void *arg))
{
eHYPLNKREFCLK e_ref_clock;
unsigned int ref_clock_hz;
static hpk_intr_cfg_s intr_cfg;
ref_clock_hz = hyplnk_input_clock();
if (ref_clock_hz == 156250000)
e_ref_clock = HYPLNK_REF_CLOCK_156P25MHZ;
else if (ref_clock_hz == 250000000)
e_ref_clock = HYPLNK_REF_CLOCK_250P00MHZ;
else if (ref_clock_hz == 312500000)
e_ref_clock = HYPLNK_REF_CLOCK_250P00MHZ;
else
return -1;
/*hyplnk dev config and link. */
hyplnk_dev_init(e_ref_clock, HYPLNK_LANES_SPEED_DEFAULT);
/*----------------------initialize hyplnk interupt--------------------------*/
/*map Hyperlink error/status interrupt to interrupt vector 0*/
intr_cfg.sts_int_enable = 1;
intr_cfg.sts_int_vec= 0;
/*interrupt to remote DSP to interrupt vector 1*/
intr_cfg.int_event_cntl[HW_EVENT_FOR_INT_CKDZ].si_en = 1;
intr_cfg.int_event_cntl[HW_EVENT_FOR_INT_CKDZ].mps = 0;
intr_cfg.int_event_cntl[HW_EVENT_FOR_INT_CKDZ].vector = 1;
/*generate interrupt packet to remote DSP when local interrupt event happens*/
intr_cfg.int_local= 0;
/*route interrupt packet from remote DSP to interrupt pending register*/
intr_cfg.int2cfg = 1;
hyplnk_dev_intr_init(&intr_cfg);
g_hyplnk_intr_usr_cfg.arg = arg;
g_hyplnk_intr_usr_cfg.intr_handle = intr_handle;
hyplnk_install_isr(&g_hyplnk_intr_usr_cfg, __hyplnk_intr_isr);
return 0;
}
/*
* ck: 64 seg, and per seg map 4M addr space
*/
int hyplnk_addr_map(hpk_addr_cfg_s *addr_map)
{
int i, j;
hpk_seg_info_s *seg_info;
unsigned int temp_len;
int drv_seg_num;
int drv_seg_index;
Hpk_Address_Map_s drv_addr_mapp;
if (!addr_map) {
hpk_debug("fail: hpylnk addr map == NULL \n");
return -1;
}
if (addr_map->seg_num > 64) {
hpk_debug("fail: hyplnk addr map seg more than 64.\n");
return -2;
}
memset(&drv_addr_mapp, 0, sizeof drv_addr_mapp);
/* open whole 256MB window */
drv_addr_mapp.tx_priv_id_ovl = TX_PRIVID_OVL_ADDR_31_28;
drv_addr_mapp.tx_addr_mask = TX_ADDR_MASK_0x0FFFFFFF;
drv_addr_mapp.rx_priv_id_sel = RX_PRIVID_SEL_ADDR_31_28;
drv_addr_mapp.rx_seg_sel = RX_SEG_SEL_ADDR_27_22; /*[27:22] -> 64 drv seg*/
/* seg config */
for (i = 0; i < addr_map->seg_num; ++i) {
seg_info = &addr_map->seg_info[i];
/* local addr must be 4M algin*/
if (seg_info->local_addr & 0x3FFFFF) {
hpk_debug("fail: hyplnk seg map local addr is 4M algin \n");
return -3;
}
/* remote addr must be 64K algin. */
if (seg_info->remote_addr & 0xFFFF) {
hpk_debug("fail: hyplnk seg map remote addr is 64K algin \n");
return -4;
}
/* seg map leng must be 512B algin. */
temp_len = seg_info->map_leng;
if (temp_len & 0x1F) {
hpk_debug("fail: hyplnk seg map leng is 512B algin \n");
return -5;
}
drv_seg_num = (temp_len > 0x400000) ? (temp_len >> 22) : 1;
drv_seg_index = (seg_info->local_addr & 0xFFFFFFF) >> 22; /*local addr: [27: 22] is drv seg index*/
for (j = 0; j < drv_seg_num; ++j) {
if (drv_seg_index + j > 64) {
hpk_debug("fail: hyplnk seg map total leng is more than 256MB \n");
return -6;
}
drv_addr_mapp.rx_addr_segs[drv_seg_index + j].Seg_Base_Addr = seg_info->remote_addr + (j << 22);
drv_addr_mapp.rx_addr_segs[drv_seg_index + j].Seg_Length = \
(temp_len > 0x400000) ? RX_SEG_LEN_0x0_0040_0000 : __hyplnk_seg_len_type(temp_len);
temp_len -= 0x400000;
}
}
#define MPU_HPYLNK_DRV_PRIVID 13
#define MPU_HPYLNK_SUP_RPIVID 14
for (i = 0; i < 8; ++i)
drv_addr_mapp.rx_priv_id_map[i] = MPU_HPYLNK_DRV_PRIVID;
for (i = 8; i < 16; ++i)
drv_addr_mapp.rx_priv_id_map[i] = MPU_HPYLNK_SUP_RPIVID;
return hyplnk_dev_addr_map(&drv_addr_mapp);
}
int hyplnk_send_intr_remote(void )
{
hyplnk_dev_trigger_intr(HW_EVENT_FOR_INT_CKDZ);
return 0;
}

23
packages/vsky/libdsp/hyplnk/hyplnk_func.h
View File

@ -0,0 +1,23 @@
#ifndef __HYPLNK_FUNC_H__
#define __HYPLNK_FUNC_H__
/* for dsp66xx */
#define HYPLNK_ADDR_SPACE_BASS 0x40000000
typedef struct hyplnk_seg_info {
unsigned int local_addr; /* addr must 4MB algin. */
unsigned int remote_addr; /* addr must 64K align. */
unsigned int map_leng; /* 512B, 1M, 2M, 4M, ... 256M. */
}hpk_seg_info_s;
typedef struct hyplnk_addr_map_cfg {
int seg_num; /* max num is 64*/
hpk_seg_info_s seg_info[64];
}hpk_addr_cfg_s;
int hyplnk_init(void *arg, void (*intr_handle)(void *arg));
int hyplnk_addr_map(hpk_addr_cfg_s *addr_map);
int hyplnk_send_intr_remote(void );
#endif //__HYPLNK_FUNC_H__

34
packages/vsky/libdsp/hyplnk/hyplnk_intr.c
View File

@ -0,0 +1,34 @@
#include <ti/sysbios/family/c64p/EventCombiner.h>
#include <ti/sysbios/family/c66/tci66xx/CpIntc.h>
#include <ti/csl/cslr_device.h>
#include "hyplnk_intr.h"
#define HOST_INTR_NUM_CIC_OUT 16
void hyplnk_install_isr(void *arg, void (*isr)(void *arg))
{
int32_t eventId;
/* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
CpIntc_dispatchPlug(CSL_INTC0_VUSR_INT_O, (CpIntc_FuncPtr)isr, (UArg)arg, TRUE);
/* The configuration is for CPINTC0. We map system interrupt 111 to Host Interrupt 16. */
CpIntc_mapSysIntToHostInt(0, CSL_INTC0_VUSR_INT_O, HOST_INTR_NUM_CIC_OUT);
/* Enable the Host Interrupt. */
CpIntc_enableHostInt(0, HOST_INTR_NUM_CIC_OUT);
/* Enable the System Interrupt */
CpIntc_enableSysInt(0, CSL_INTC0_VUSR_INT_O);
/* Get the event id associated with the host interrupt. */
eventId = CpIntc_getEventId(HOST_INTR_NUM_CIC_OUT);
/* Plug the CPINTC Dispatcher. */
EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, HOST_INTR_NUM_CIC_OUT, TRUE);
}

6
packages/vsky/libdsp/hyplnk/hyplnk_intr.h
View File

@ -0,0 +1,6 @@
#ifndef _HYPLNK_INTR_H__
#define _HYPLNK_INTR_H__
void hyplnk_install_isr(void *arg, void (*isr)(void *arg));
#endif //

3
packages/vsky/libdsp/inc/board.h
View File

@ -17,8 +17,7 @@ extern "C" {
unsigned int board_input_clock();
unsigned int sgmii_input_clock();
unsigned int srio_input_clock();
unsigned int hyperlink_input_clock();
unsigned int hyperlink_speed();
unsigned int hyplnk_input_clock();
/*
* get mac address.

2
packages/vsky/libdsp/inc/power_ctrl.h
View File

@ -12,4 +12,6 @@ void power_up_domains(void );
void power_up_srio(void );
void power_up_hyplnk(void );
#endif /* POWER_CTRL_H_ */

13
packages/vsky/libdsp/srio/srio_func.c
View File

@ -318,8 +318,6 @@ int srio_dev_init(uint16_t node_id, void *arg, HWIISRPFUNC doorbell_isr, HWIISRP
srio_cfg_s srio_device_cfg;
//system resource mgr init
//srio module power on
power_up_srio();
/*srio dev init*/
__init_srio_device_cfg(&srio_device_cfg, node_id);
@ -575,20 +573,21 @@ int srio_msg_write(srio_msg_packet_s *msg)
int srio_msg_read(srio_msg_packet_s *msg)
{
int32_t num_bytes;
Cppi_HostDesc *ptrHostDesc;
Srio_SockAddrInfo from;
int32_t num_bytes;
uint8_t *rx_data_payload;
num_bytes = Srio_sockRecv (msgSocket, (Srio_DrvBuffer*)&msg->data, &from);
num_bytes = Srio_sockRecv (msgSocket, (Srio_DrvBuffer*)&rx_data_payload, &from);
if (num_bytes < 0)
return -1;
msg->node_id = from.type11.id;
msg->mbox = from.type11.mbox;
msg->len = num_bytes;
msg->data = rx_data_payload;
/* Cleanup the received packet. */
Srio_freeRxDrvBuffer(msgSocket, ptrHostDesc);
Srio_freeRxDrvBuffer(msgSocket, (Srio_DrvBuffer)rx_data_payload);
return 0;
}

13
samples/hyperlink/.ccsproject
View File

@ -1,13 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?ccsproject version="1.0"?>
<projectOptions>
<deviceVariant value="TMS320C66XX.TMS320C6678"/>
<deviceFamily value="C6000"/>
<deviceEndianness value="little"/>
<codegenToolVersion value="7.4.20"/>
<isElfFormat value="true"/>
<connection value="common/targetdb/connections/SD560V2USB_Connection.xml"/>
<rts value="libc.a"/>
<templateProperties value="id=com.ti.common.project.core.emptyProjectTemplate,"/>
</projectOptions>

147
samples/hyperlink/.cproject
View File

@ -1,147 +0,0 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule configRelations="2" moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.ti.ccstudio.buildDefinitions.C6000.Debug.23733135">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.23733135" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<extensions>
<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="com.ti.ccstudio.errorparser.CoffErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.LinkErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="com.ti.ccstudio.errorparser.AsmErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactExtension="out" artifactName="${ProjName}" buildProperties="" cleanCommand="${CG_CLEAN_CMD}" description="" id="com.ti.ccstudio.buildDefinitions.C6000.Debug.23733135" name="Debug" parent="com.ti.ccstudio.buildDefinitions.C6000.Debug">
<folderInfo id="com.ti.ccstudio.buildDefinitions.C6000.Debug.23733135." name="/" resourcePath="">
<toolChain id="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain.1306022243" name="TI Build Tools" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.DebugToolchain" targetTool="com.ti.ccstudio.buildDefinitions.C6000_7.4.exe.linkerDebug.859141050">
<option id="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS.144347401" superClass="com.ti.ccstudio.buildDefinitions.core.OPT_TAGS" valueType="stringList">
<listOptionValue builtIn="false" value="DEVICE_CONFIGURATION_ID=TMS320C66XX.TMS320C6678"/>
<listOptionValue builtIn="false" value="DEVICE_ENDIANNESS=little"/>
<listOptionValue builtIn="false" value="OUTPUT_FORMAT=ELF"/>
<listOptionValue builtIn="false" value="CCS_MBS_VERSION=5.1.0.01"/>
<listOptionValue builtIn="false" value="RUNTIME_SUPPORT_LIBRARY=libc.a"/>
<listOptionValue builtIn="false" value="OUTPUT_TYPE=executable"/>
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179
samples/hyperlink/hyplink.c
View File

@ -1,179 +0,0 @@
/*
* hyplink_init.c
*
* Created on: 2018-10-29
* Author: Administrator
*/
#include "hyplink.h"
#include <csl_bootcfgaux.h>
#include <stdint.h>
#include <stdio.h>
#include <cslr_vusr.h>
//#define DDR_SPACE_ACCESSED_BY_HYPERLINK 0x88000000
CSL_VusrRegs * gpHyperLinkRegs = (CSL_VusrRegs *)CSL_MCM_CONFIG_REGS;
CSL_BootcfgRegs * gpBootCfgRegs = (CSL_BootcfgRegs *)CSL_BOOT_CFG_REGS;
int pllm, vo = 0, rate;
void vsky_serdes_init( uint32_t ref_Mhz,uint32_t speed_GHz)
{
switch (ref_Mhz) {
case 156250: {
switch(speed_GHz) {
case 1250000:
pllm = 0x3C; // 0100 0000 (16x --> 2.5G PLL out clock)
vo = 0;
break;
default:
pllm = 0x50; // 0101 0000 (20x --> 3.125 PLL out clock)
vo = 0;
break;
}
} break;
case 250000: {
switch(speed_GHz) {
case 1250000:
pllm = 0x28; // 0010 1000 (10x --> 2.5G PLL out clock)
vo = 0;
break;
default:
pllm = 0x50; // 0011 0010 (12.5x --> 3.125 PLL out clock)
vo = 0;
break;
}
} break;
case 312500: {
switch(speed_GHz) {
case 1250000:
pllm = 0x20; // 0010 0000 (8x --> 2.5G PLL out clock)
vo = 0;
break;
default:
pllm = 0x28; // 0010 1000 (10x --> 3.125 PLL out clock)
vo = 0;
break;
}
} break;
default:
break;
}
switch (speed_GHz) {
case 1250000:
rate = 0x3; // 11b (one data sample is taken every 2 pll output);
break;
case 3125000:
rate = 0x2; // 10b (one data sample is taken every 1 pll output);
break;
case 6250000:
rate = 0x1; // 01b (two data sample is taken every 1 pll output);
break;
case 12500000:
rate = 0x0; // 00b (four data sample is taken every 1 pll output);
break;
default:
break;
}
}
void hyperlink_addr_map(HyperLink_Address_Map * addr_map)
{
int i;
gpHyperLinkRegs->TX_SEL_CTL =
(addr_map->tx_addr_mask<<CSL_VUSR_TX_SEL_CTL_TXIGNMSK_SHIFT)
|(addr_map->tx_priv_id_ovl<<CSL_VUSR_TX_SEL_CTL_TXPRIVIDOVL_SHIFT);
gpHyperLinkRegs->RX_SEL_CTL =
(addr_map->rx_seg_sel<<CSL_VUSR_RX_SEL_CTL_RXSEGSEL_SHIFT)
|(addr_map->rx_priv_id_sel<<CSL_VUSR_RX_SEL_CTL_RXPRIVIDSEL_SHIFT);
for(i= 0; i< 16; i++)
{
gpHyperLinkRegs->RX_PRIV_IDX= i;
gpHyperLinkRegs->RX_PRIV_VAL= addr_map->rx_priv_id_map[i];
}
for(i= 0; i< 64; i++)
{
gpHyperLinkRegs->RX_SEG_IDX= i;
gpHyperLinkRegs->RX_SEG_VAL=
addr_map->rx_addr_segs[i].Seg_Base_Addr
|addr_map->rx_addr_segs[i].Seg_Length;
}
}
void hyperlink_SerdesCfg ()
{
volatile uint16_t pllcfg;
uint32_t cfgrx_default = 0x0046c485,cfgtx_default = 0x001c8f85;
volatile uint32_t cfgrx,cfgtx;
CSL_BootCfgUnlockKicker();
vsky_serdes_init(hyperlink_input_clock(),hyperlink_speed());
pllcfg = (1<<0)|(vo <<9)|((Uint16)(pllm << 1));
cfgrx = cfgrx_default | (rate << 4);
cfgtx = cfgtx_default | (rate << 4);
CSL_BootCfgSetVUSRConfigPLL(pllcfg);
CSL_BootCfgSetVUSRRxConfig (0, cfgrx);
CSL_BootCfgSetVUSRRxConfig (1, cfgrx);
CSL_BootCfgSetVUSRRxConfig (2, cfgrx);
CSL_BootCfgSetVUSRRxConfig (3, cfgrx);
CSL_BootCfgSetVUSRTxConfig (0, cfgtx);
CSL_BootCfgSetVUSRTxConfig (1, cfgtx);
CSL_BootCfgSetVUSRTxConfig (2, cfgtx);
CSL_BootCfgSetVUSRTxConfig (3, cfgtx);
CSL_BootCfgLockKicker();
} /* hyplnkExampleSerdesCfg */
void hyperlink_init(HyperLink_Config * hyperLink_cfg)
{
gpHyperLinkRegs->PWR =
(7<<CSL_VUSR_PWR_H2L_SHIFT)
|(7<<CSL_VUSR_PWR_L2H_SHIFT)
|(1<<CSL_VUSR_PWR_PWC_SHIFT)
|(1<<CSL_VUSR_PWR_QUADLANE_SHIFT)
|(0<<CSL_VUSR_PWR_ZEROLANE_SHIFT)
|(0<<CSL_VUSR_PWR_SINGLELANE_SHIFT);
/*enable operation*/
gpHyperLinkRegs->CTL &= ~(CSL_VUSR_CTL_SERIAL_STOP_MASK);
hyperlink_addr_map(&hyperLink_cfg->address_map);
//KeyStone_HyperLink_Interrupt_init(&hyperLink_cfg->interrupt_cfg);
/*tell all receivers to ignore close to the first 3uS of data at beginning of training sequence*/
gpHyperLinkRegs->SERDES_CTL_STS1= 0xFFFF0000;
//PC TEST
//gpHyperLinkRegs->SERDES_CTL_STS4= 0x000F0000;//No SERDES sleep for four lane mode operation
//hyperLinkSerdesRegs = (SerdesRegs *)&gpBootCfgRegs->VUSR_CFGPLL;
hyperlink_SerdesCfg ();
//Wait_Hyperlink_PLL_Lock();
while ((gpBootCfgRegs->STS_VUSR & 0x00000001) != 0x00000001);
//ck: test add
/*---------wait for link status OK-------------*/
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_SERIAL_HALT_MASK);
while(gpHyperLinkRegs->STS&CSL_VUSR_STS_PLL_UNLOCK_MASK);
while(0==(gpHyperLinkRegs->STS&CSL_VUSR_STS_LINK_MASK));
while(0==(gpHyperLinkRegs->LINK_STS&CSL_VUSR_LINK_STS_RX_ONE_ID_MASK));
/*after initialization, change the delay to default value to improve performance*/
//gpHyperLinkRegs->SERDES_CTL_STS1= 0x092E0000;
}
void hyperlink_write(void * restrict dst,void * restrict src,uint32_t count)
{
memcpy(dst, src, count);
}

258
samples/hyperlink/hyplink.h
View File

@ -1,258 +0,0 @@
/*
* hyplink_init.h
*
* Created on: 2018-10-29
* Author: Administrator
*/
#ifndef HYPLINK_INIT_H_
#define HYPLINK_INIT_H_
#include <stdint.h>
#include <stdio.h>
#define NUM_MPS 8 /*Number of supported Micro Processor*/
#define HYPERLINK_INPUT_CLCK_156p25 156.25
#define HYPERLINK_INPUT_CLCK_250 250
#define HYPERLINK_INPUT_CLCK_312p5 312.5
#define HYPERLINK_SPEED_1p25 1.25
#define HYPERLINK_SPEED_3p125 3.125
#define HYPERLINK_SPEED_6p25 6.25
#define HYPERLINK_SPEED_12p5 12.5
/*select which bits of the RxAddress are used to select which
Segment/Length array element value to Add/Check to the Address signal.*/
uint32_t hyperlink_input_clock();
uint32_t hyperlink_speed();
typedef enum
{
RX_SEG_SEL_0, /*always use 0 as index to lookup segment/length table*/
RX_SEG_SEL_ADDR_22_17,
RX_SEG_SEL_ADDR_23_18,
RX_SEG_SEL_ADDR_24_19,
RX_SEG_SEL_ADDR_25_20,
RX_SEG_SEL_ADDR_26_21,
RX_SEG_SEL_ADDR_27_22,
RX_SEG_SEL_ADDR_28_23,
RX_SEG_SEL_ADDR_29_24,
RX_SEG_SEL_ADDR_30_25,
RX_SEG_SEL_ADDR_31_26,
RX_SEG_SEL_ADDR_31_27,
RX_SEG_SEL_ADDR_31_28,
RX_SEG_SEL_ADDR_31_29,
RX_SEG_SEL_ADDR_31_30,
RX_SEG_SEL_ADDR_31
}HyperLink_RxSegSel;
typedef enum
{
RX_SEG_LEN_0x0_0000_0002,
RX_SEG_LEN_0x0_0000_0004,
RX_SEG_LEN_0x0_0000_0008,
RX_SEG_LEN_0x0_0000_0010,
RX_SEG_LEN_0x0_0000_0020,
RX_SEG_LEN_0x0_0000_0040,
RX_SEG_LEN_0x0_0000_0080,
RX_SEG_LEN_0x0_0000_0100,
RX_SEG_LEN_0x0_0000_0200,
RX_SEG_LEN_0x0_0000_0400,
RX_SEG_LEN_0x0_0000_0800,
RX_SEG_LEN_0x0_0000_1000,
RX_SEG_LEN_0x0_0000_2000,
RX_SEG_LEN_0x0_0000_4000,
RX_SEG_LEN_0x0_0000_8000,
RX_SEG_LEN_0x0_0001_0000,
RX_SEG_LEN_0x0_0002_0000,
RX_SEG_LEN_0x0_0004_0000,
RX_SEG_LEN_0x0_0008_0000,
RX_SEG_LEN_0x0_0010_0000,
RX_SEG_LEN_0x0_0020_0000,
RX_SEG_LEN_0x0_0040_0000,
RX_SEG_LEN_0x0_0080_0000,
RX_SEG_LEN_0x0_0100_0000,
RX_SEG_LEN_0x0_0200_0000,
RX_SEG_LEN_0x0_0400_0000,
RX_SEG_LEN_0x0_0800_0000,
RX_SEG_LEN_0x0_1000_0000,
RX_SEG_LEN_0x0_2000_0000,
RX_SEG_LEN_0x0_4000_0000,
RX_SEG_LEN_0x0_8000_0000,
RX_SEG_LEN_0x1_0000_0000
}HyperLink_RxSegLen;
typedef struct{
uint32_t Seg_Base_Addr; /*low 16 bits must be 0*/
HyperLink_RxSegLen Seg_Length; /*must be power of 2, 0~0x100000000*/
}HyperLink_Rx_Address_Segment;
/*select which bits of the RxAddress are used to select which PrivID
array element value to drive to the PrivID signal.*/
typedef enum
{
RX_PRIVID_0, /*always use 0 as privID*/
RX_PRIVID_SEL_ADDR_20_17,
RX_PRIVID_SEL_ADDR_21_18,
RX_PRIVID_SEL_ADDR_22_19,
RX_PRIVID_SEL_ADDR_23_20,
RX_PRIVID_SEL_ADDR_24_21,
RX_PRIVID_SEL_ADDR_25_22,
RX_PRIVID_SEL_ADDR_26_23,
RX_PRIVID_SEL_ADDR_27_24,
RX_PRIVID_SEL_ADDR_28_25,
RX_PRIVID_SEL_ADDR_29_26,
RX_PRIVID_SEL_ADDR_30_27,
RX_PRIVID_SEL_ADDR_31_28,
RX_PRIVID_SEL_ADDR_31_29,
RX_PRIVID_SEL_ADDR_31_30,
RX_PRIVID_SEL_ADDR_31
}HyperLink_RxPrivIdSel;
/*Specifies where the PrivID is placed in the outgoing TxAddress.*/
typedef enum
{
TX_PRIVID_NO_OVERLAY,
TX_PRIVID_OVL_ADDR_20_17,
TX_PRIVID_OVL_ADDR_21_18,
TX_PRIVID_OVL_ADDR_22_19,
TX_PRIVID_OVL_ADDR_23_20,
TX_PRIVID_OVL_ADDR_24_21,
TX_PRIVID_OVL_ADDR_25_22,
TX_PRIVID_OVL_ADDR_26_23,
TX_PRIVID_OVL_ADDR_27_24,
TX_PRIVID_OVL_ADDR_28_25,
TX_PRIVID_OVL_ADDR_29_26,
TX_PRIVID_OVL_ADDR_30_27,
TX_PRIVID_OVL_ADDR_31_28,
TX_PRIVID_OVL_ADDR_31_29,
TX_PRIVID_OVL_ADDR_31_30,
TX_PRIVID_OVL_ADDR_31
}HyperLink_TxPrivIdOvl;
/*create the mask that is logically anded to the incoming address to create
the address sent to the remote.*/
typedef enum
{
TX_ADDR_MASK_0x0001FFFF,
TX_ADDR_MASK_0x0003FFFF,
TX_ADDR_MASK_0x0007FFFF,
TX_ADDR_MASK_0x000FFFFF,
TX_ADDR_MASK_0x001FFFFF,
TX_ADDR_MASK_0x003FFFFF,
TX_ADDR_MASK_0x007FFFFF,
TX_ADDR_MASK_0x00FFFFFF,
TX_ADDR_MASK_0x01FFFFFF,
TX_ADDR_MASK_0x03FFFFFF,
TX_ADDR_MASK_0x07FFFFFF,
TX_ADDR_MASK_0x0FFFFFFF,
TX_ADDR_MASK_0x1FFFFFFF,
TX_ADDR_MASK_0x3FFFFFFF,
TX_ADDR_MASK_0x7FFFFFFF,
TX_ADDR_MASK_0xFFFFFFFF
}HyperLink_TxAddrMask;
typedef struct{
/*create the mask that is logically anded to the incoming address to create
the address sent to the remote.*/
HyperLink_TxAddrMask tx_addr_mask;
/*Specifies where the PrivID is placed in the outgoing TxAddress.*/
HyperLink_TxPrivIdOvl tx_priv_id_ovl;
/*The rxsegsel value is used to select which bits of the RxAddress
are used to select which Segment/Length array element value to
Add/Check to the Address signal.*/
HyperLink_RxSegSel rx_seg_sel;
HyperLink_Rx_Address_Segment rx_addr_segs[64];
/*The rxprividsel value is used to select which bits of the
RxAddress are used to select which PrivID array element
value to drive to the PrivID signal.*/
HyperLink_RxPrivIdSel rx_priv_id_sel;
uint8_t rx_priv_id_map[16];
}HyperLink_Address_Map;
typedef struct{
/*Interrupt Enable. When set, this bit indicates that interrupts detected
on the Hyperlink_int_i[icidx] pin should be should be forwarded to the
below mps:vector interrupt vector.*/
uint8_t Int_en;
/*Interrupt Type. When set, this bit indicates that the
Hyperlink_int_i[icidx] interrupt is pulsed. When clear, this bit
indicates that Hyperlink_int_i[icidx] is level sensitive.*/
uint8_t Int_type;
/*Interrupt Polarity When set, this bit indicates that the
Hyperlink_int_i[icidx)] interrupt is active low. When clear, this
bit indicates that Hyperlink_int_i[icidx] is active high*/
uint8_t Int_pol;
/*Software Interrupt Enable indicate if this interrupt can be issued
via software writing to the Generate Soft Interrupt
Value register for this SoftInt[icidx].*/
uint8_t si_en;
uint8_t mps; /*MicroProcessor Select*/
/*When the local device has int2Local =1, this field indicates which bit
of interrupt pending register to set. When the local device has
int2local =0, this field is transferred to the remote device, which is
used to indicate which bit of the interrupt pending register to set in
the remote device. */
uint8_t vector;
}HyperLink_int_event_control;
typedef struct{
/*Interrupt Local. This bit determines whether interrupts are posted in
the Interrupt Status/Clear Register or forwarded via the serial interface.
When set, interrupts are posted in the Interrupt Status/Clear Register and
the Hyperlink_intpls_o and Hyperlink_intlvl_o pins are asserted.
When clear, interrupts are forwarded out the serial interface to the remote
device.*/
uint8_t int_local;
/*Interrupt Enable. This bit causes HyperLink module status interrupts to
be posted to the Interrupt Pending/Set Register*/
uint8_t sts_int_enable;
/*Interrupt Vector. This field indicates which bit in the Interrupt
Pending/Set Register is set for HyperLink module status interrupts.*/
uint8_t sts_int_vec;
/*The Interrupt pending register can be set by the remote
device through the interrupt packet, when the int2cfg is set to 1.
When int2cfg is clear, the interrupt status is extracted from the
received interrupt packet and written to the register indicated by
the Interrupt Pointer Register for the particular micro processor
select (MPS) value.*/
uint8_t int2cfg;
HyperLink_int_event_control int_event_cntl[64];
/*The Interrupt Pointer Registers typically map to microprocessor
interrupt controller set registers which get set to a one to interrupt
that processor.*/
uint8_t int_set_register_pointer[NUM_MPS];
}HyperLink_Interrupt_Cfg;
typedef enum
{
HyperLink_LOOPBACK_DISABLE = 0,
HyperLink_LOOPBACK
}HyperLink_Loopback_Mode;
typedef struct {
HyperLink_Address_Map address_map;
HyperLink_Interrupt_Cfg interrupt_cfg;
HyperLink_Loopback_Mode loopback_mode;
//SerdesSetup_4links serdes_cfg;
} HyperLink_Config;
void hyperlink_write(void * restrict dst, void * restrict src,uint32_t count);
void hyperlink_init(HyperLink_Config * hyperLink_cfg);
#endif /* HYPLINK_INIT_H_ */

137
samples/hyperlink/main.c
View File

@ -1,137 +0,0 @@
/*
* main.c
*
* Created on: 2018-10-30
* Author: Administrator
*/
#include <stdint.h>
#include "tsc.h"
#include "hyplink.h"
#include "power_ctrl.h"
#define HyperLink_SL2_ADDR (0x4c200000)
#define HyperLink_LL2_ADDR (0x00850000)
#define HW_EVENT_FOR_INT_TEST 0
HyperLink_Config hyperLink_cfg;
static int CORE_NUM = 1;
uint32_t board_input_clock()
{
return 100000000;
}
uint32_t hyperlink_input_clock()
{
return 156250;
}
uint32_t hyperlink_speed()
{
return 3125000;
}
void hyperlink_config(uint32_t DDR_SPACE_ACCESSED_BY_HYPERLINK)
{
int iPrvId,iSeg;
/*----------------Initialize Hyperlink address map----------------------*/
/*use 28 bits address for TX (256 MB) */
hyperLink_cfg.address_map.tx_addr_mask = TX_ADDR_MASK_0x0FFFFFFF;
/*overlay PrivID to higher 4 bits of address for TX*/
hyperLink_cfg.address_map.tx_priv_id_ovl = TX_PRIVID_OVL_ADDR_31_28;
/*Select higher 4 bits of address as PrivID for RX*/
hyperLink_cfg.address_map.rx_priv_id_sel = RX_PRIVID_SEL_ADDR_31_28;
/*map remote PrviID 0~7 to loccal ID 13*/
hyperLink_cfg.address_map.rx_priv_id_map[0] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[1] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[2] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[3] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[4] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[5] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[6] = 13;
hyperLink_cfg.address_map.rx_priv_id_map[7] = 13;
/*map remote PrviID 8~15 to loccal ID 14*/
hyperLink_cfg.address_map.rx_priv_id_map[8] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[9] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[10] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[11] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[12] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[13] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[14] = 14;
hyperLink_cfg.address_map.rx_priv_id_map[15] = 14;
/*use bit 24~29 (4 bits (24~27) MSB address, 2 bits (28~29)
remote PriviID) as index to lookup segment/length table*/
hyperLink_cfg.address_map.rx_seg_sel = RX_SEG_SEL_ADDR_29_24;
/*map local memory into the same segments for all PrivID (remote masters)*/
for(iSeg= 0; iSeg<8; iSeg++)
for(iPrvId=0; iPrvId<4; iPrvId++)
{
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Base_Addr=
0x10000000+iSeg*0x01000000;
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Length=
RX_SEG_LEN_0x0_0100_0000;
}
/*map a part of DDR3 into the same segments for all PrvID (remote masters)*/
for(iSeg= 8; iSeg<0xC; iSeg++)
for(iPrvId=0; iPrvId<4; iPrvId++)
{
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Base_Addr=
DDR_SPACE_ACCESSED_BY_HYPERLINK+(iSeg-8)*0x01000000;
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Length=
RX_SEG_LEN_0x0_0100_0000;
}
/*map SL2 into same segement for all PrvID (remote masters)*/
for(iPrvId=0; iPrvId<4; iPrvId++)
{
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|0xC].Seg_Base_Addr=
0x0C000000;
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|0xC].Seg_Length=
RX_SEG_LEN_0x0_0100_0000;
}
/*map different DDR3 sections into the segements
of different PrvID (remote masters)*/
for(iPrvId=0; iPrvId<4; iPrvId++)
for(iSeg= 0xD; iSeg<=0xF; iSeg++)
{
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Base_Addr=
DDR_SPACE_ACCESSED_BY_HYPERLINK+0x04000000+(iPrvId*3+iSeg-0xD)*0x01000000;
hyperLink_cfg.address_map.rx_addr_segs[(iPrvId<<4)|iSeg].Seg_Length=
RX_SEG_LEN_0x0_0100_0000;
}
hyperlink_init(&hyperLink_cfg);
}
void main()
{
tsc_init();
power_up_domains();
hyperlink_config(0x88000000);
if(CORE_NUM)
{
int i;
uint32_t *dst,*src;
dst = (uint32_t *)HyperLink_SL2_ADDR;
src = (uint32_t *)HyperLink_LL2_ADDR;
for(i=0;i<(1024/8);i++)
{
src[i] = (uint32_t)i;
printf("*******%x\n",src);
}
hyperlink_write(dst,src,1024/8);
}
}

39
samples/hyperlink/test.cmd
View File

@ -1,39 +0,0 @@
-heap 0x800
-stack 0x1000
MEMORY
{
/* Local L2, 1MB*/
VECTORS: o = 0x00800000 l = 0x00000200
LL2_RW_DATA: o = 0x00800200 l = 0x0003FE00
/* Shared L2 2MB*/
SL2: o = 0x0C000000 l = 0x00200000
/* External DDR3, upto 2GB per core */
DDR3_CODE: o = 0x80000000 l = 0x01000000 /*set memory protection attribitue as execution only*/
DDR3_R_DATA: o = 0x81000000 l = 0x01000000 /*set memory protection attribitue as read only*/
DDR3_RW_DATA: o = 0x82000000 l = 0x06000000 /*set memory protection attribitue as read/write*/
}
SECTIONS
{
vecs > VECTORS
.text > SL2
.cinit > SL2
.const > SL2
.switch > SL2
.stack > LL2_RW_DATA
GROUP
{
.neardata
.rodata
.bss
} > LL2_RW_DATA
.far > LL2_RW_DATA
.fardata > LL2_RW_DATA
.cio > LL2_RW_DATA
.sysmem > LL2_RW_DATA
}

1
samples/srio/.cproject
View File

@ -40,6 +40,7 @@
<option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.INCLUDE_PATH.705675147" name="Add dir to #include search path (--include_path, -I)" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.INCLUDE_PATH" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/inc}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/srio}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/hyplnk}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${CG_TOOL_ROOT}/include&quot;"/>
</option>
<option id="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.LANGUAGE_MODE.242979748" name="Language mode" superClass="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.LANGUAGE_MODE" value="com.ti.ccstudio.buildDefinitions.C6000_7.4.compilerID.LANGUAGE_MODE.RELAXED_ANSI" valueType="enumerated"/>

5
samples/srio/.project
View File

@ -41,6 +41,11 @@
<type>2</type>
<locationURI>$%7BDSPKIT%7D/vsky/libdsp/emac</locationURI>
</link>
<link>
<name>hyplnk</name>
<type>2</type>
<location>E:/dsp/6678_066/server/libdsp/packages/vsky/libdsp/hyplnk</location>
</link>
<link>
<name>inc</name>
<type>2</type>

5
samples/srio/src/board.c
View File

@ -23,6 +23,11 @@ unsigned int srio_input_clock()
return BOARD_INPUT_REF_CLOCK_SRIO;
}
unsigned int hyplnk_input_clock()
{
return BOARD_INPUT_REF_CLOCK_HYPLNK;
}
const char *emac_mac_address(int port)
{
static uint8_t emac_ddr[2][6] = {{0x22, 0x33, 0x44, 0x55, 0x66, 0x80},

74
samples/srio/src/hyplnk.c
View File

@ -0,0 +1,74 @@
/*
* hyplnk.c
*
* Created on: 2018-11-15
* Author: Administrator
*/
#include <stdio.h>
#include <string.h>
#include "hyplnk_func.h"
typedef struct hyplnk_test {
int sem;
hpk_addr_cfg_s map_table;
}hyplnk_test_s;
extern int g_master;
static hyplnk_test_s _hpk_test;
static void __hyplnk_intr(void *arg)
{
hyplnk_test_s *ht = (hyplnk_test_s *)arg;
ht->sem += 1;
}
int hyplnk_task()
{
_hpk_test.sem = 0;
hyplnk_init(&_hpk_test, __hyplnk_intr);
/* local remote leng
* 0x40000000 -> 0x0C3000000 4M
* 0x40100000 -> 0xB00000000 252M
* */
_hpk_test.map_table.seg_info[0].local_addr = 0x40000000;
_hpk_test.map_table.seg_info[0].remote_addr = 0x0C300000; //msmc
_hpk_test.map_table.seg_info[0].map_leng = 0x400000; //4M
_hpk_test.map_table.seg_info[1].local_addr = 0x40400000;
_hpk_test.map_table.seg_info[1].remote_addr = 0xB0000000; //ddr
_hpk_test.map_table.seg_info[1].map_leng = 0x0FC00000; //252M
_hpk_test.map_table.seg_num = 2;
hyplnk_addr_map(&_hpk_test.map_table);
printf("hyplnk func init complete ... \n");
if (g_master) {
printf("master: send data to remote... \n");
memset((void *)0x40000000, 0xA1, _hpk_test.map_table.seg_info[0].map_leng);
memset((void *)0x40400000, 0xA2, _hpk_test.map_table.seg_info[1].map_leng);
printf("master: send intr to remote... \n");
hyplnk_send_intr_remote();
printf("master: wait slave ack...\n");
while(_hpk_test.sem == 0)
;
} else {
//wait recv intr
printf("slave wait recv intr\n");
while(_hpk_test.sem == 0)
;
printf("slave: send data to remote... \n");
memset((void *)0x40000000, 0xB1, _hpk_test.map_table.seg_info[0].map_leng);
memset((void *)0x40400000, 0xB2, _hpk_test.map_table.seg_info[1].map_leng);
printf("slave: send intr to remote... \n");
hyplnk_send_intr_remote();
}
printf("hpylnk test complete \n");
return 0;
}

4
samples/srio/src/main.c
View File

@ -237,7 +237,7 @@ int srio_task()
printf("slave: data verify success\n");
}
}while(0);
} while(0);
return 0;
}
@ -264,5 +264,3 @@ void main (int argc, char *argv[])
{
BIOS_start();
}

2
samples/srio/src/net.c
View File

@ -10,7 +10,7 @@
#include "tsc.h"
#include "resource_mgr.h"
#define EVMStaticIP "192.168.0.118"
#define EVMStaticIP "192.168.0.114"
#define LocalIPMask "255.255.255.0"
#define DOMAINNAME "ti_demo"

4
samples/srio/srio.cfg
View File

@ -185,6 +185,10 @@ var tskUniStackTest = Task.create("&srio_task");
tskUniStackTest.stackSize = 0x20000;
tskUniStackTest.priority = 0x3;
var tskUniStackTest = Task.create("&hyplnk_task");
tskUniStackTest.stackSize = 0x20000;
tskUniStackTest.priority = 0x3;
/*
* Create a Periodic task to handle all NDK polling functions.
* If you are using RTSC configuration with NDK 2.2 and above, this is done by default and

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