add Setting module

Signed-off-by: surenyi <surenyi82@163.com>

.gitignore

@@ -16,3 +16,4 @@ packages/ti/csl/lib
 packages/ti/csl/makefile
 packages/ti/csl/package
 packages/vsky/libdsp/driver/Uart.h
+packages/vsky/libdsp/lib

README.txt

@@ -1,4 +1,5 @@
 
 build:
+  export XDCPATH="/path/to/library;$XDCPATH"
   export XDCCGROOT=/path/to/c6000
   xdc -Pr ./packages

packages/vsky/libdsp/Settings.h

@@ -0,0 +1,271 @@
+/*
+ *  Do not modify this file; it is automatically 
+ *  generated and any modifications will be overwritten.
+ *
+ * @(#) xdc-y44
+ */
+
+/*
+ * ======== GENERATED SECTIONS ========
+ *     
+ *     PROLOGUE
+ *     INCLUDES
+ *     
+ *     INTERNAL DEFINITIONS
+ *     MODULE-WIDE CONFIGS
+ *     FUNCTION DECLARATIONS
+ *     SYSTEM FUNCTIONS
+ *     
+ *     EPILOGUE
+ *     STATE STRUCTURES
+ *     PREFIX ALIASES
+ */
+
+
+/*
+ * ======== PROLOGUE ========
+ */
+
+#ifndef vsky_libdsp_Settings__include
+#define vsky_libdsp_Settings__include
+
+#ifndef __nested__
+#define __nested__
+#define vsky_libdsp_Settings__top__
+#endif
+
+#ifdef __cplusplus
+#define __extern extern "C"
+#else
+#define __extern extern
+#endif
+
+#define vsky_libdsp_Settings___VERS 150
+
+
+/*
+ * ======== INCLUDES ========
+ */
+
+#include <xdc/std.h>
+
+#include <xdc/runtime/xdc.h>
+#include <xdc/runtime/Types.h>
+#include <vsky/libdsp/package/package.defs.h>
+
+#include <xdc/runtime/IModule.h>
+
+
+/*
+ * ======== AUXILIARY DEFINITIONS ========
+ */
+
+
+/*
+ * ======== INTERNAL DEFINITIONS ========
+ */
+
+
+/*
+ * ======== MODULE-WIDE CONFIGS ========
+ */
+
+/* Module__diagsEnabled */
+typedef xdc_Bits32 CT__vsky_libdsp_Settings_Module__diagsEnabled;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__diagsEnabled vsky_libdsp_Settings_Module__diagsEnabled__C;
+
+/* Module__diagsIncluded */
+typedef xdc_Bits32 CT__vsky_libdsp_Settings_Module__diagsIncluded;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__diagsIncluded vsky_libdsp_Settings_Module__diagsIncluded__C;
+
+/* Module__diagsMask */
+typedef xdc_Bits16* CT__vsky_libdsp_Settings_Module__diagsMask;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__diagsMask vsky_libdsp_Settings_Module__diagsMask__C;
+
+/* Module__gateObj */
+typedef xdc_Ptr CT__vsky_libdsp_Settings_Module__gateObj;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__gateObj vsky_libdsp_Settings_Module__gateObj__C;
+
+/* Module__gatePrms */
+typedef xdc_Ptr CT__vsky_libdsp_Settings_Module__gatePrms;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__gatePrms vsky_libdsp_Settings_Module__gatePrms__C;
+
+/* Module__id */
+typedef xdc_runtime_Types_ModuleId CT__vsky_libdsp_Settings_Module__id;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__id vsky_libdsp_Settings_Module__id__C;
+
+/* Module__loggerDefined */
+typedef xdc_Bool CT__vsky_libdsp_Settings_Module__loggerDefined;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerDefined vsky_libdsp_Settings_Module__loggerDefined__C;
+
+/* Module__loggerObj */
+typedef xdc_Ptr CT__vsky_libdsp_Settings_Module__loggerObj;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerObj vsky_libdsp_Settings_Module__loggerObj__C;
+
+/* Module__loggerFxn0 */
+typedef xdc_runtime_Types_LoggerFxn0 CT__vsky_libdsp_Settings_Module__loggerFxn0;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerFxn0 vsky_libdsp_Settings_Module__loggerFxn0__C;
+
+/* Module__loggerFxn1 */
+typedef xdc_runtime_Types_LoggerFxn1 CT__vsky_libdsp_Settings_Module__loggerFxn1;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerFxn1 vsky_libdsp_Settings_Module__loggerFxn1__C;
+
+/* Module__loggerFxn2 */
+typedef xdc_runtime_Types_LoggerFxn2 CT__vsky_libdsp_Settings_Module__loggerFxn2;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerFxn2 vsky_libdsp_Settings_Module__loggerFxn2__C;
+
+/* Module__loggerFxn4 */
+typedef xdc_runtime_Types_LoggerFxn4 CT__vsky_libdsp_Settings_Module__loggerFxn4;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerFxn4 vsky_libdsp_Settings_Module__loggerFxn4__C;
+
+/* Module__loggerFxn8 */
+typedef xdc_runtime_Types_LoggerFxn8 CT__vsky_libdsp_Settings_Module__loggerFxn8;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__loggerFxn8 vsky_libdsp_Settings_Module__loggerFxn8__C;
+
+/* Module__startupDoneFxn */
+typedef xdc_Bool (*CT__vsky_libdsp_Settings_Module__startupDoneFxn)(void);
+__extern __FAR__ const CT__vsky_libdsp_Settings_Module__startupDoneFxn vsky_libdsp_Settings_Module__startupDoneFxn__C;
+
+/* Object__count */
+typedef xdc_Int CT__vsky_libdsp_Settings_Object__count;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Object__count vsky_libdsp_Settings_Object__count__C;
+
+/* Object__heap */
+typedef xdc_runtime_IHeap_Handle CT__vsky_libdsp_Settings_Object__heap;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Object__heap vsky_libdsp_Settings_Object__heap__C;
+
+/* Object__sizeof */
+typedef xdc_SizeT CT__vsky_libdsp_Settings_Object__sizeof;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Object__sizeof vsky_libdsp_Settings_Object__sizeof__C;
+
+/* Object__table */
+typedef xdc_Ptr CT__vsky_libdsp_Settings_Object__table;
+__extern __FAR__ const CT__vsky_libdsp_Settings_Object__table vsky_libdsp_Settings_Object__table__C;
+
+/* freq */
+#ifdef vsky_libdsp_Settings_freq__D
+#define vsky_libdsp_Settings_freq (vsky_libdsp_Settings_freq__D)
+#else
+#define vsky_libdsp_Settings_freq (vsky_libdsp_Settings_freq__C)
+typedef xdc_UInt32 CT__vsky_libdsp_Settings_freq;
+__extern __FAR__ const CT__vsky_libdsp_Settings_freq vsky_libdsp_Settings_freq__C;
+#endif
+
+/* clock */
+#ifdef vsky_libdsp_Settings_clock__D
+#define vsky_libdsp_Settings_clock (vsky_libdsp_Settings_clock__D)
+#else
+#define vsky_libdsp_Settings_clock (vsky_libdsp_Settings_clock__C)
+typedef xdc_UInt32 CT__vsky_libdsp_Settings_clock;
+__extern __FAR__ const CT__vsky_libdsp_Settings_clock vsky_libdsp_Settings_clock__C;
+#endif
+
+
+/*
+ * ======== FUNCTION DECLARATIONS ========
+ */
+
+/* Module_startup */
+#define vsky_libdsp_Settings_Module_startup( state ) (-1)
+
+/* Module__startupDone__S */
+xdc__CODESECT(vsky_libdsp_Settings_Module__startupDone__S, "vsky_libdsp_Settings_Module__startupDone")
+__extern xdc_Bool vsky_libdsp_Settings_Module__startupDone__S( void );
+
+/* getCoreFreq__E */
+#define vsky_libdsp_Settings_getCoreFreq vsky_libdsp_Settings_getCoreFreq__E
+xdc__CODESECT(vsky_libdsp_Settings_getCoreFreq__E, "vsky_libdsp_Settings_getCoreFreq")
+__extern xdc_UInt32 vsky_libdsp_Settings_getCoreFreq__E( void );
+xdc__CODESECT(vsky_libdsp_Settings_getCoreFreq__F, "vsky_libdsp_Settings_getCoreFreq")
+__extern xdc_UInt32 vsky_libdsp_Settings_getCoreFreq__F( void );
+__extern xdc_UInt32 vsky_libdsp_Settings_getCoreFreq__R( void );
+
+
+/*
+ * ======== SYSTEM FUNCTIONS ========
+ */
+
+/* Module_startupDone */
+#define vsky_libdsp_Settings_Module_startupDone() vsky_libdsp_Settings_Module__startupDone__S()
+
+/* Object_heap */
+#define vsky_libdsp_Settings_Object_heap() vsky_libdsp_Settings_Object__heap__C
+
+/* Module_heap */
+#define vsky_libdsp_Settings_Module_heap() vsky_libdsp_Settings_Object__heap__C
+
+/* Module_id */
+static inline CT__vsky_libdsp_Settings_Module__id vsky_libdsp_Settings_Module_id( void ) 
+{
+    return vsky_libdsp_Settings_Module__id__C;
+}
+
+/* Module_hasMask */
+static inline xdc_Bool vsky_libdsp_Settings_Module_hasMask( void ) 
+{
+    return vsky_libdsp_Settings_Module__diagsMask__C != NULL;
+}
+
+/* Module_getMask */
+static inline xdc_Bits16 vsky_libdsp_Settings_Module_getMask( void ) 
+{
+    return vsky_libdsp_Settings_Module__diagsMask__C != NULL ? *vsky_libdsp_Settings_Module__diagsMask__C : 0;
+}
+
+/* Module_setMask */
+static inline xdc_Void vsky_libdsp_Settings_Module_setMask( xdc_Bits16 mask ) 
+{
+    if (vsky_libdsp_Settings_Module__diagsMask__C != NULL) *vsky_libdsp_Settings_Module__diagsMask__C = mask;
+}
+
+
+/*
+ * ======== EPILOGUE ========
+ */
+
+#ifdef vsky_libdsp_Settings__top__
+#undef __nested__
+#endif
+
+#endif /* vsky_libdsp_Settings__include */
+
+
+/*
+ * ======== STATE STRUCTURES ========
+ */
+
+#if defined(__config__) || (!defined(__nested__) && defined(vsky_libdsp_Settings__internalaccess))
+
+#ifndef vsky_libdsp_Settings__include_state
+#define vsky_libdsp_Settings__include_state
+
+
+#endif /* vsky_libdsp_Settings__include_state */
+
+#endif
+
+/*
+ * ======== PREFIX ALIASES ========
+ */
+
+#if !defined(__nested__) && !defined(vsky_libdsp_Settings__nolocalnames)
+
+#ifndef vsky_libdsp_Settings__localnames__done
+#define vsky_libdsp_Settings__localnames__done
+
+/* module prefix */
+#define Settings_freq vsky_libdsp_Settings_freq
+#define Settings_clock vsky_libdsp_Settings_clock
+#define Settings_getCoreFreq vsky_libdsp_Settings_getCoreFreq
+#define Settings_Module_name vsky_libdsp_Settings_Module_name
+#define Settings_Module_id vsky_libdsp_Settings_Module_id
+#define Settings_Module_startup vsky_libdsp_Settings_Module_startup
+#define Settings_Module_startupDone vsky_libdsp_Settings_Module_startupDone
+#define Settings_Module_hasMask vsky_libdsp_Settings_Module_hasMask
+#define Settings_Module_getMask vsky_libdsp_Settings_Module_getMask
+#define Settings_Module_setMask vsky_libdsp_Settings_Module_setMask
+#define Settings_Object_heap vsky_libdsp_Settings_Object_heap
+#define Settings_Module_heap vsky_libdsp_Settings_Module_heap
+
+#endif /* vsky_libdsp_Settings__localnames__done */
+#endif

packages/vsky/libdsp/Settings.xdc

@@ -0,0 +1,6 @@
+module Settings {
+    config UInt32 freq  = 1000000000;
+    config UInt32 clock = 100000000;
+    UInt32 getCoreFreq();
+}
+

packages/vsky/libdsp/driver/Uart.xdc

@@ -1,6 +1,25 @@
+import vsky.libdsp.Settings;
+
 module Uart {
-    Int32  init(UInt32 clock);
+    /*
+     * default baudrate.
+     */
+    config UInt32 baudrate = 115200;
+
+    /*!
+     * init uart
+     */
+    Int32  init();
+    /*!
+     * set baudrate.
+     */
     void   setBaudrate(UInt32 bps);
+
+    /*!
+     * puts
+     */
+    Void puts(String s);
+
     UInt32 getBaudrate();
     Int32  get();
     Void   put(Int32 dt);

packages/vsky/libdsp/driver/uart.c

@@ -1,26 +1,20 @@
 #include <ti/csl/csl_chip.h>
 #include <ti/csl/cslr_uart.h>
+#include <vsky/libdsp/Settings.h>
+#include "package/internal/Uart.xdc.h"
 
-#define DEFAULT_RATE (115200)
 #define hUartRegs ((CSL_UartRegs*)CSL_UART_REGS)
 
-static Uint32 __clock;
-
 static Uint16 __to_regrate(Uint32 bps)
 {
-    return (Uint16)(__clock / (bps * 16));
+//    Uint32 uc = 166666666;
+    Uint32 uc = Settings_freq / 6;
+
+    return (Uint16)(uc / (bps * 16));
 }
 
-Int32 Uart_init(Uint32 clk)
+Int32 Uart_init()
 {
-    Uint16 rate;
-
-    if (clk <= 0) {
-        return -1;
-    }
-
-    __clock = clk;
-
     //      Allows access to the divisor latches of the baud generator during a 
     // read or write operation (DLL and DLH)
     CSL_FINS (hUartRegs->LCR, UART_LCR_DLAB, CSL_UART_LCR_DLAB_ENABLE);
@@ -34,9 +28,8 @@ Int32 Uart_init(Uint32 clk)
     CSL_FINS (hUartRegs->LCR, UART_LCR_PEN,  CSL_UART_LCR_PEN_DISABLE);    
 
     // Set the baudrate,for accessing LCR[7] should be enable 
-    rate = __to_regrate(DEFAULT_RATE);
-    hUartRegs->DLL  = rate & 0xff;
-    hUartRegs->DLH  = (rate >> 8) & 0xff;
+    hUartRegs->DLL  = 0x30;
+    hUartRegs->DLH  = 0x00;
 
     // Allows access to the receiver buffer register (RBR), 
     // the transmitter holding register (THR), and the
@@ -99,6 +92,8 @@ Int32 Uart_init(Uint32 clk)
     CSL_FINS (hUartRegs->FCR, UART_FCR_DMAMODE1, CSL_UART_FCR_DMAMODE1_DISABLE);
     CSL_FINS (hUartRegs->FCR, UART_FCR_RXFIFTL,  CSL_UART_FCR_RXFIFTL_CHAR1);
 
+    Uart_setBaudrate(Uart_baudrate);
+
     return 0;
 }
 
@@ -109,8 +104,8 @@ void Uart_setBaudrate(Uint32 bps)
     hUartRegs->LCR = 0x80;
 
     // Set the baudrate,for accessing LCR[7] should be enable 
-    hUartRegs->DLL  =  bps & 0xff;
-    hUartRegs->DLH  =  (bps >> 8) & 0xff;
+    hUartRegs->DLL  =  rate & 0xff;
+    hUartRegs->DLH  =  (rate >> 8) & 0xff;
     hUartRegs->LCR = 0x03;
 }
 
@@ -118,13 +113,14 @@ Uint32 Uart_getBaudrate(void)
 {
     Uint32 rate = 0;
     Uint16 reg;
+    Uint32 uc = Settings_freq / 6;
 
     hUartRegs->LCR = 0x80;
     // Read the baudrate 
     reg = (hUartRegs->DLL & 0xff) | ((hUartRegs->DLH & 0xff)<< 8);
     hUartRegs->LCR = 0x03;
     if (reg > 0) 
-        rate = __clock / (reg * 16);
+        rate = uc / (reg * 16);
     return rate;
 }
 
@@ -158,3 +154,15 @@ Bool Uart_isReady(void)
 	return (dr);
 }
 
+Void Uart_puts(String s)
+{
+    Char ch;
+    if (s) {
+        while ((ch = *s) != '\0') {
+            Uart_put(ch);
+            ++s;
+        }
+    }
+}
+
+

packages/vsky/libdsp/inc/_regs.h

@@ -0,0 +1,48 @@
+#ifndef __DRVREGS_H__
+#define __DRVREGS_H__
+
+#define   PLL1_BASE           0x02310000
+#define   PLL1_STAT           (*(unsigned int*)(PLL1_BASE + 0x13C))   // STAT control
+#define   PLLM_REG            (*((volatile uint32_t *) 0x02310110))
+#define   PREDIV_REG          (*((volatile uint32_t *) 0x02310114))
+#define   PLLDIV2_REG         (*((volatile uint32_t *) 0x0231011C))
+#define   PLLDIV5_REG         (*((volatile uint32_t *) 0x02310164))
+#define   PLLDIV8_REG         (*((volatile uint32_t *) 0x02310170))
+
+struct PLLHwInfo {
+    /** \brief Divider Enable/Disable
+     *  \param CSL_BitMask32
+     */
+    CSL_BitMask32 divEnable;
+    /** \brief PLL Multiplier
+     *  \param Uint32
+     */
+    Uint32        pllM;
+    /** \brief PLL Divider 2
+     *  \param Uint32
+     */
+    Uint32        pllDiv2;
+    /** \brief PLL Divider 5
+     *  \param Uint32
+     */
+    Uint32        pllDiv5;
+    /** \brief PLL Divider 8
+     *  \param Uint32
+     */
+    Uint32        pllDiv8;    
+    /** \brief pre Divider value
+     *  \param Uint32
+     */
+    Uint32        preDiv;
+    /** \brief post Divider value
+     *  \param Uint32
+     */
+    Uint32        postDiv;
+    /** \brief Setup that can be used for future implementation
+     *  \param void*
+     */     
+    void*         extendSetup;
+};
+
+#endif
+

packages/vsky/libdsp/package.bld

@@ -1,9 +1,26 @@
 Pkg.otherFiles = [
     "package.bld",
     "package.xdc",
-    "package.inc"
+    "package.inc",
+    "Settings.xdc",
 ];
 
+var objFiles = [
+    "settings.c",
+];
+
+for (var i = 0; i < Build.targets.length; i++) {
+    var targ = Build.targets[i];
+    var libName = "dsputils";
+
+    var libOptions = {
+        incs: libdspPathInclude,
+    };
+
+    var lib = Pkg.addLibrary("lib/" + libName, targ, libOptions);
+    lib.addObjects(objFiles);
+}
+
 Pkg.attrs.exportSrc = true;
 Pkg.attrs.exportCfg = true;
 

packages/vsky/libdsp/package.xdc

@@ -2,5 +2,6 @@
  * Package specification file for libdsp
  */
 package vsky.libdsp {
+    module Settings;
 }
 

packages/vsky/libdsp/settings.c

@@ -0,0 +1,62 @@
+#include <ti/csl/csl_error.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_bootcfgAux.h>
+#include "package/internal/Settings.xdc.h"
+#include "_regs.h"
+
+static void __delay(uint32_t ix)
+{
+    while (ix--) {
+        asm("   NOP");
+    }
+}
+
+static CSL_Status CorePllcGetHwSetup (struct PLLHwInfo *hwSetup)
+{
+    CSL_Status       status   = CSL_SOK;
+    volatile uint32_t i, loopCount;
+
+    /* Unlock the Boot Config */
+    CSL_BootCfgUnlockKicker();
+
+    hwSetup->divEnable = 0;
+
+    hwSetup->pllM       = (PLLM_REG & 0x3F);
+    hwSetup->preDiv     = PREDIV_REG;
+    hwSetup->pllDiv2    = PLLDIV2_REG ;
+    hwSetup->pllDiv5    = PLLDIV5_REG;
+    hwSetup->pllDiv8    = PLLDIV8_REG;
+
+    /* wait for the GOSTAT, but don't trap if lock is never read */
+    for (i = 0; i < 100; i++) {
+        __delay(300);
+        if ( (PLL1_STAT & 0x00000001) == 0 ) {
+            break;
+        }
+    }
+    if (i == 100) {
+        return CSL_ESYS_FAIL;
+    }
+
+    return status;
+}
+
+UInt32 Settings_getCoreFreq()
+{
+    CSL_Status   status;
+    struct PLLHwInfo   hwSetupRead;
+    UInt32      dsp_freq;
+    
+    status = CorePllcGetHwSetup (&hwSetupRead);
+
+    if (status != CSL_SOK) {
+        return (uint32_t)-1;
+    } else {
+        /* Compute the real dsp freq (*100) */
+        dsp_freq = (hwSetupRead.pllM + 1)>> 1;
+        dsp_freq = (dsp_freq * Settings_clock)/(hwSetupRead.preDiv + 1);        
+    }
+
+    return (dsp_freq);
+}
+