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arm-trusted-firmware/plat/arm/board/arm_fpga/fpga_def.h

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plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede <oli.swede@arm.com> Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
5 years ago
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/utils_def.h>
#ifndef FPGA_DEF_H
#define FPGA_DEF_H
/*
plat/arm/board/arm_fpga: Enable port for alternative cluster configurations This change is part of the goal of enabling the port to be compatible with multiple FPGA images. The BL31 port that is uploaded as a payload to the FPGA with an image should cater for a wide variety of system configurations. This patch makes the necessary changes to enable it to function with images whose cluster configurations may be larger (either by utilizing more clusters, more CPUs per cluster, more threads in each CPU, or a combination) than the initial image being used for testing. As part of this, the hard-coded values that configure the size of the array describing the topology of the power domain tree are increased to max. 8 clusters, max. 8 cores per cluster &amp; max 4 threads per core. This ensures the port works with cluster configurations up to these sizes. When there are too many entries for the number of available PEs, e.g. if there is a variable number of CPUs between clusters, then there will be empty entries in the array. This is permitted and the PSCI library will still function as expected. While this increases its size, this shouldn&#39;t be an issue in the context of the size of BL31, and is worth the trade-off for the extra compatibility. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
5 years ago
* These are set to large values to account for images describing systems with
* larger cluster configurations.
*
* For cases where the number of clusters, cores or threads is smaller than a
* maximum value below, this does not affect the PSCI functionality as any PEs
* that are present will still be indexed appropriately regardless of any empty
* entries in the array used to represent the topology.
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
5 years ago
*/
arm_fpga: Add support for topology self-discovery As secondary cores show up, they populate an array to announce themselves so plat_core_pos_by_mpidr() can return an invalid COREID code for any non-existing MPIDR that it is queried about. The Power Domain Tree Description is populated with a topology based on the maximum harcoded values. Signed-off-by: Javier Almansa Sobrino &lt;javier.almansasobrino@arm.com&gt; Change-Id: I8fd64761a2296714ce0f37c46544f3e6f13b5f61
5 years ago
arm_fpga: Support more CPU clusters The maximum number of clusters is currently set to 2, which is quite limiting. As there are FPGA images with 4 clusters, let&#39;s increase the limit to 4. Change-Id: I9a85ca07ebbd2a018ad9668536d867ad6b75e537 Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
4 years ago
#define FPGA_MAX_CLUSTER_COUNT 4
plat/arm/board/arm_fpga: Enable port for alternative cluster configurations This change is part of the goal of enabling the port to be compatible with multiple FPGA images. The BL31 port that is uploaded as a payload to the FPGA with an image should cater for a wide variety of system configurations. This patch makes the necessary changes to enable it to function with images whose cluster configurations may be larger (either by utilizing more clusters, more CPUs per cluster, more threads in each CPU, or a combination) than the initial image being used for testing. As part of this, the hard-coded values that configure the size of the array describing the topology of the power domain tree are increased to max. 8 clusters, max. 8 cores per cluster &amp; max 4 threads per core. This ensures the port works with cluster configurations up to these sizes. When there are too many entries for the number of available PEs, e.g. if there is a variable number of CPUs between clusters, then there will be empty entries in the array. This is permitted and the PSCI library will still function as expected. While this increases its size, this shouldn&#39;t be an issue in the context of the size of BL31, and is worth the trade-off for the extra compatibility. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I7d4ae1e20b2e99fdbac428d122a2cf9445394363
5 years ago
#define FPGA_MAX_CPUS_PER_CLUSTER 8
#define FPGA_MAX_PE_PER_CPU 4
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
5 years ago
#define FPGA_PRIMARY_CPU 0x0
/*******************************************************************************
* FPGA image memory map related constants
******************************************************************************/
arm_fpga: Read UART address from DT The arm_fpga port requires a DTB, to launch a BL33 payload. To make this port more flexible, we can also use the information in the DT to configure the console driver. For a start, find the DT node pointed to by the stdout-path property, and read the base address from there. This assumes for now that the stdout-path points to a PL011 UART. This allows to remove platform specific addresses from the image. We keep the original base address for the crash console. Change-Id: I46a990de2315f81cae4d7913ae99a07b0bec5cb1 Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
5 years ago
/*
* UART base address, just for the crash console, as a fallback.
* The actual console UART address is taken from the DT.
*/
#define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
5 years ago
arm_fpga: Read generic timer counter frequency from DT The ARM Generic Timer DT binding describes an (optional) property to declare the counter frequency. Its usage is normally discouraged, as the value should be read from the CNTFRQ_EL0 system register. However in our case we can use it to program this register in the first place, which avoids us to hard code a counter frequency into the code. We keep some default value in, if the DT lacks that property for whatever reason. Change-Id: I5b71176db413f904f21eb16f3302fbb799cb0305 Signed-off-by: Andre Przywara &lt;andre.przywara@arm.com&gt;
5 years ago
#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
plat/arm/board/arm_fpga: Initialize the System Counter This sets the frequency of the system counter so that the Delay Timer driver programs the correct value to CNTCRL. This value depends on the FPGA image being used, and is 10MHz for the initial test image. Once configured, the BL31 platform setup sequence then enables the system counter. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: Ieb036a36fd990f350b5953357424a255b8ac5d5a
5 years ago
plat/arm/board/arm_fpga: Enable basic BL31 port for an FPGA image This adds the minimal functions and definitions to create a basic BL31 port for an initial FPGA image, in order for the port to be uploaded to one the FPGA boards operated by an internal group within Arm, such that BL31 runs as a payload for an image. Future changes will enable the port for a wide range of system configurations running on the FPGA boards to ensure compatibility with multiple FPGA images. It is expected that this will replace the FPGA fork of the Linux kernel bootwrapper by performing similar secure-world initialization and setup through the use of drivers and other well-established methods, before passing control to the kernel, which will act as the BL33 payload and run in EL2NS. This change introduces a basic, loadable port with the console initialized by setting the baud rate and base address of the UART as configured by the Zeus image. It is a BL31-only port, and RESET_TO_BL31 is enabled to reflect this. Signed-off-by: Oliver Swede &lt;oli.swede@arm.com&gt; Change-Id: I1817ad81be00afddcdbbda1ab70eb697203178e2
5 years ago
#endif