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238 lines
7.6 KiB
238 lines
7.6 KiB
9 years ago
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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.globl flush_dcache_range
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.globl clean_dcache_range
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.globl inv_dcache_range
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.globl dcsw_op_louis
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.globl dcsw_op_all
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.globl dcsw_op_level1
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.globl dcsw_op_level2
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.globl dcsw_op_level3
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/*
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* This macro can be used for implementing various data cache operations `op`
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*/
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.macro do_dcache_maintenance_by_mva op, coproc, opc1, CRn, CRm, opc2
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dcache_line_size r2, r3
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add r1, r0, r1
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sub r3, r2, #1
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bic r0, r0, r3
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loop_\op:
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stcopr r0, \coproc, \opc1, \CRn, \CRm, \opc2
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add r0, r0, r2
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cmp r0, r1
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blo loop_\op
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dsb sy
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bx lr
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.endm
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/* ------------------------------------------
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* Clean+Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func flush_dcache_range
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do_dcache_maintenance_by_mva cimvac, DCCIMVAC
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endfunc flush_dcache_range
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/* ------------------------------------------
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* Clean from base address till size.
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* 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func clean_dcache_range
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do_dcache_maintenance_by_mva cmvac, DCCMVAC
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endfunc clean_dcache_range
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/* ------------------------------------------
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* Invalidate from base address till
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* size. 'r0' = addr, 'r1' = size
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* ------------------------------------------
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*/
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func inv_dcache_range
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do_dcache_maintenance_by_mva imvac, DCIMVAC
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endfunc inv_dcache_range
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/* ----------------------------------------------------------------
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* Data cache operations by set/way to the level specified
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* r1: The cache level to begin operation from
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* r2: clidr_el1
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* r3: The last cache level to operate on
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* and will carry out the operation on each data cache from level 0
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* to the level in r3 in sequence
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*
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* The dcsw_op macro sets up the r2 and r3 parameters based on
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* clidr_el1 cache information before invoking the main function
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* ----------------------------------------------------------------
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*/
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.macro dcsw_op shift, fw, ls
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ldcopr r2, CLIDR
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ubfx r3, r2, \shift, \fw
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lsl r3, r3, \ls
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mov r1, #0
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b do_dcsw_op
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.endm
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func do_dcsw_op
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push {r4-r12,lr}
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adr r11, dcsw_loop_table // compute cache op based on the operation type
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add r6, r11, r0, lsl #3 // cache op is 2x32-bit instructions
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loop1:
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add r10, r1, r1, LSR #1 // Work out 3x current cache level
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mov r12, r2, LSR r10 // extract cache type bits from clidr
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and r12, r12, #7 // mask the bits for current cache only
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cmp r12, #2 // see what cache we have at this level
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blt level_done // no cache or only instruction cache at this level
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stcopr r1, CSSELR // select current cache level in csselr
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isb // isb to sych the new cssr&csidr
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ldcopr r12, CCSIDR // read the new ccsidr
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and r10, r12, #7 // extract the length of the cache lines
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add r10, r10, #4 // add 4 (r10 = line length offset)
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ubfx r4, r12, #3, #10 // r4 = maximum way number (right aligned)
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clz r5, r4 // r5 = the bit position of the way size increment
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mov r9, r4 // r9 working copy of the aligned max way number
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loop2:
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ubfx r7, r12, #13, #15 // r7 = max set number (right aligned)
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loop3:
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orr r0, r1, r9, LSL r5 // factor in the way number and cache level into r0
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orr r0, r0, r7, LSL r10 // factor in the set number
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blx r6
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subs r7, r7, #1 // decrement the set number
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bge loop3
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subs r9, r9, #1 // decrement the way number
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bge loop2
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level_done:
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add r1, r1, #2 // increment the cache number
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cmp r3, r1
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dsb sy // ensure completion of previous cache maintenance instruction
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bgt loop1
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mov r6, #0
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stcopr r6, CSSELR //select cache level 0 in csselr
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dsb sy
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isb
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pop {r4-r12,pc}
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dcsw_loop_table:
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stcopr r0, DCISW
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bx lr
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stcopr r0, DCCISW
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bx lr
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stcopr r0, DCCSW
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bx lr
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endfunc do_dcsw_op
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoU.
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*
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* The function requires :
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_louis
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dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_louis
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/* ---------------------------------------------------------------
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* Data cache operations by set/way till PoC.
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*
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* The function requires :
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_all
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dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
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endfunc dcsw_op_all
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/* ---------------------------------------------------------------
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* Helper macro for data cache operations by set/way for the
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* level specified
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* ---------------------------------------------------------------
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*/
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.macro dcsw_op_level level
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ldcopr r2, CLIDR
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mov r3, \level
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sub r1, r3, #2
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b do_dcsw_op
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.endm
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 1 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level1
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dcsw_op_level #(1 << LEVEL_SHIFT)
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endfunc dcsw_op_level1
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 2 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level2
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dcsw_op_level #(2 << LEVEL_SHIFT)
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endfunc dcsw_op_level2
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/* ---------------------------------------------------------------
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* Data cache operations by set/way for level 3 cache
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*
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* The main function, do_dcsw_op requires:
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* r0: The operation type (DC_OP_ISW, DC_OP_CISW, DC_OP_CSW),
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* as defined in arch.h
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* ---------------------------------------------------------------
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*/
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func dcsw_op_level3
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dcsw_op_level #(3 << LEVEL_SHIFT)
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endfunc dcsw_op_level3
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