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77 lines
1.7 KiB
77 lines
1.7 KiB
3 years ago
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/*
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* Copyright 2018-2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLAT_DEF_H
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#define PLAT_DEF_H
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#include <arch.h>
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#include <cortex_a72.h>
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/*
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* Required without TBBR.
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* To include the defines for DDR PHY
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* Images.
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*/
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#include <tbbr_img_def.h>
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#include <policy.h>
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#include <soc.h>
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#define NXP_SYSCLK_FREQ 100000000
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#define NXP_DDRCLK_FREQ 100000000
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/* UART related definition */
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#define NXP_CONSOLE_ADDR NXP_UART_ADDR
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#define NXP_CONSOLE_BAUDRATE 115200
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#define NXP_SPD_EEPROM0 0x51
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/* Size of cacheable stacks */
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#if defined(IMAGE_BL2)
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#if defined(TRUSTED_BOARD_BOOT)
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#define PLATFORM_STACK_SIZE 0x2000
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#else
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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#elif defined(IMAGE_BL31)
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#define PLATFORM_STACK_SIZE 0x1000
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#endif
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/* SD block buffer */
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#define NXP_SD_BLOCK_BUF_SIZE (0xC000)
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#ifdef SD_BOOT
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
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- NXP_SD_BLOCK_BUF_SIZE)
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#else
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#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
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#endif
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#define BL2_TEXT_LIMIT (BL2_LIMIT)
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/* IO defines as needed by IO driver framework */
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#define MAX_IO_DEVICES 4
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#define MAX_IO_BLOCK_DEVICES 1
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#define MAX_IO_HANDLES 4
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#define BL31_WDOG_SEC 89
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/*
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* Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_LS_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE)
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/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
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#define PLAT_LS_G0_IRQ_PROPS(grp) \
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INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(15, GIC_HIGHEST_SEC_PRIORITY, grp, \
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GIC_INTR_CFG_LEVEL)
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#endif /* PLAT_DEF_H */
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