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arm-trusted-firmware/plat/qti/msm8916/msm8916_gicv2.c

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feat(msm8916): setup hardware for non-secure world Booting e.g. Linux in the non-secure world does not work with the msm8916 port yet because essential hardware is not made available to the non-secure world. Add more platform initialization to: - Initialize the GICv2 and mark secure interrupts. Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2 register address in platform_def.h to avoid a failing assert() because of a (hardware) mistake in Qualcomm's GICv2 implementation. - Make a timer frame available to the non-secure world. The "Qualcomm Timer" (QTMR) implements the ARM generic timer specification, so the standard defines (CNTACR_BASE etc) can be used. - Make parts of the "APCS" register region available to the non-secure world, e.g. for CPU frequency control implemented in Linux. - Initialize a platform-specific register to route all SMMU context bank interrupts to the non-secure interrupt pin, since all control of the SMMUs is left up to the non-secure world for now. Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
3 years ago
/*
* Copyright (c) 2021, Stephan Gerhold <stephan@gerhold.net>
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <drivers/arm/gicv2.h>
#include <lib/mmio.h>
#include "msm8916_gicv2.h"
#include <msm8916_mmap.h>
feat(msm8916): add Test Secure Payload (TSP) port Use the new shared msm8916 setup code to easily allow compiling the Test Secure Payload (TSP) for the msm8916 platform. Unlike BL31, TSP only calls msm8916_platform_setup() but not msm8916_configure() because this is already done in BL31. Change-Id: I3225ef9e61387d49870e9759ffd5b899a8805961 Signed-off-by: Stephan Gerhold &lt;stephan@gerhold.net&gt;
2 years ago
#include <platform_def.h>
feat(msm8916): setup hardware for non-secure world Booting e.g. Linux in the non-secure world does not work with the msm8916 port yet because essential hardware is not made available to the non-secure world. Add more platform initialization to: - Initialize the GICv2 and mark secure interrupts. Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2 register address in platform_def.h to avoid a failing assert() because of a (hardware) mistake in Qualcomm&#39;s GICv2 implementation. - Make a timer frame available to the non-secure world. The &#34;Qualcomm Timer&#34; (QTMR) implements the ARM generic timer specification, so the standard defines (CNTACR_BASE etc) can be used. - Make parts of the &#34;APCS&#34; register region available to the non-secure world, e.g. for CPU frequency control implemented in Linux. - Initialize a platform-specific register to route all SMMU context bank interrupts to the non-secure interrupt pin, since all control of the SMMUs is left up to the non-secure world for now. Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d Signed-off-by: Stephan Gerhold &lt;stephan@gerhold.net&gt;
3 years ago
#define IRQ_SEC_SGI_0 8
#define IRQ_SEC_SGI_1 9
#define IRQ_SEC_SGI_2 10
#define IRQ_SEC_SGI_3 11
#define IRQ_SEC_SGI_4 12
#define IRQ_SEC_SGI_5 13
#define IRQ_SEC_SGI_6 14
#define IRQ_SEC_SGI_7 15
static const interrupt_prop_t msm8916_interrupt_props[] = {
INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
};
static const gicv2_driver_data_t msm8916_gic_data = {
.gicd_base = APCS_QGIC2_GICD,
.gicc_base = APCS_QGIC2_GICC,
.interrupt_props = msm8916_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(msm8916_interrupt_props),
};
void msm8916_gicv2_init(void)
{
gicv2_driver_init(&msm8916_gic_data);
refactor(msm8916): separate common platform setup code In preparation of adding BL32 support for the msm8916 platform (AArch32/SP_MIN and TSP), separate the common platform setup code into shared msm8916_setup.c and msm8916_config.c files which can be called from both BL31 and BL32. msm8916_setup.c contains the relevant shared code for BL31/SP_MIN/TSP, while msm8916_config.c is cold boot configuration code that is only relevant for BL31 and SP_MIN (but not TSP). No functional change. Change-Id: I055522d5ad8c03dfb8e09236dc47dd383a480e95 Signed-off-by: Stephan Gerhold &lt;stephan@gerhold.net&gt;
2 years ago
}
void msm8916_gicv2_configure(void)
{
feat(msm8916): setup hardware for non-secure world Booting e.g. Linux in the non-secure world does not work with the msm8916 port yet because essential hardware is not made available to the non-secure world. Add more platform initialization to: - Initialize the GICv2 and mark secure interrupts. Only secure SGIs/PPIs so far. Override the GICD_PIDR2_GICV2 register address in platform_def.h to avoid a failing assert() because of a (hardware) mistake in Qualcomm&#39;s GICv2 implementation. - Make a timer frame available to the non-secure world. The &#34;Qualcomm Timer&#34; (QTMR) implements the ARM generic timer specification, so the standard defines (CNTACR_BASE etc) can be used. - Make parts of the &#34;APCS&#34; register region available to the non-secure world, e.g. for CPU frequency control implemented in Linux. - Initialize a platform-specific register to route all SMMU context bank interrupts to the non-secure interrupt pin, since all control of the SMMUs is left up to the non-secure world for now. Change-Id: Icf676437b8e329dead06658e177107dfd0ba4f9d Signed-off-by: Stephan Gerhold &lt;stephan@gerhold.net&gt;
3 years ago
gicv2_distif_init();
gicv2_pcpu_distif_init();
gicv2_cpuif_enable();
}