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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <el3_common_macros.S>
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.globl bl2_entrypoint
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.globl bl2_vector_table
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.globl bl2_el3_run_image
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.globl bl2_run_next_image
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func bl2_entrypoint
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/* Save arguments x0-x3 from previous Boot loader */
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mov x20, x0
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mov x21, x1
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mov x22, x2
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mov x23, x3
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el3_entrypoint_common \
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_init_sctlr=1 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=bl2_el3_exceptions
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/*
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* Restore parameters of boot rom
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*/
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mov x0, x20
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mov x1, x21
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mov x2, x22
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mov x3, x23
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bl bl2_el3_early_platform_setup
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bl bl2_el3_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2_entrypoint
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func bl2_run_next_image
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mov x20,x0
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/*
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* MMU needs to be disabled because both BL2 and BL31 execute
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* in EL3, and therefore share the same address space.
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* BL31 will initialize the address space according to its
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* own requirement.
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*/
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bl disable_mmu_icache_el3
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tlbi alle3
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bl bl2_el3_plat_prepare_exit
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ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
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msr elr_el3, x0
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msr spsr_el3, x1
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ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
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ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
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ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
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ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
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eret
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endfunc bl2_run_next_image
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