arm-trusted-firmware/fdts/fvp-base-gicv3-psci-common.dtsi

/*
 * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <services/sdei_flags.h>

#define LEVEL	0
#define EDGE	2
#define SDEI_NORMAL	0x70
#define HIGHEST_SEC	0

/memreserve/ 0x80000000 0x00010000;

/ {
};

/ {
	model = "FVP Base";
	compatible = "arm,vfp-base", "arm,vexpress";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

#if (ENABLE_RME == 1)
	chosen { bootargs = "mem=1G console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";};
#else
	chosen {};
#endif

	aliases {
		serial0 = &v2m_serial0;
		serial1 = &v2m_serial1;
		serial2 = &v2m_serial2;
		serial3 = &v2m_serial3;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
		method = "smc";
		cpu_suspend = <0xc4000001>;
		cpu_off = <0x84000002>;
		cpu_on = <0xc4000003>;
		sys_poweroff = <0x84000008>;
		sys_reset = <0x84000009>;
		max-pwr-lvl = <2>;
	};

#if SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF
	firmware {
#if SDEI_IN_FCONF
		sdei {
			compatible = "arm,sdei-1.0";
			method = "smc";
			private_event_count = <3>;
			shared_event_count = <3>;
			/*
			 * Each event descriptor has typically 3 fields:
			 * 1. Event number
			 * 2. Interrupt number the event is bound to or
			 *    if event is dynamic, specified as SDEI_DYN_IRQ
			 * 3. Bit map of event flags
			 */
			private_events =	<1000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
						<1001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
						<1002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
			shared_events =		<2000 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
						<2001 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>,
						<2002 SDEI_DYN_IRQ SDEI_MAPF_DYNAMIC>;
		};
#endif /* SDEI_IN_FCONF */

#if SEC_INT_DESC_IN_FCONF
		sec_interrupts {
			compatible = "arm,secure_interrupt_desc";
			/* Number of G0 and G1 secure interrupts defined by the platform */
			g0_intr_cnt = <2>;
			g1s_intr_cnt = <9>;
			/*
			 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
			 * terminology. Each interrupt property descriptor has 3 fields:
			 * 1. Interrupt number
			 * 2. Interrupt priority
			 * 3. Type of interrupt (Edge or Level configured)
			 */
			g0_intr_desc =	< 8 SDEI_NORMAL EDGE>,
					<14 HIGHEST_SEC EDGE>;

			g1s_intr_desc =	< 9 HIGHEST_SEC EDGE>,
					<10 HIGHEST_SEC EDGE>,
					<11 HIGHEST_SEC EDGE>,
					<12 HIGHEST_SEC EDGE>,
					<13 HIGHEST_SEC EDGE>,
					<15 HIGHEST_SEC EDGE>,
					<29 HIGHEST_SEC LEVEL>,
					<56 HIGHEST_SEC LEVEL>,
					<57 HIGHEST_SEC LEVEL>;
		};
#endif /* SEC_INT_DESC_IN_FCONF */
	};
#endif /* SDEI_IN_FCONF || SEC_INT_DESC_IN_FCONF */

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU_MAP

		idle-states {
			entry-method = "arm,psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <40>;
				exit-latency-us = <100>;
				min-residency-us = <150>;
			};

			CLUSTER_SLEEP_0: cluster-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <500>;
				exit-latency-us = <1000>;
				min-residency-us = <2500>;
			};
		};

		CPUS

		L2_0: l2-cache0 {
			compatible = "cache";
		};
	};

	memory@80000000 {
		device_type = "memory";
#if (ENABLE_RME == 1)
		reg = <0x00000000 0x80000000 0 0x7C000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
#else
		reg = <0x00000000 0x80000000 0 0x7F000000>,
		      <0x00000008 0x80000000 0 0x80000000>;
#endif
	};

	gic: interrupt-controller@2f000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		interrupt-controller;
		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
		      <0x0 0x2f100000 0 0x200000>,	// GICR
		      <0x0 0x2c000000 0 0x2000>,	// GICC
		      <0x0 0x2c010000 0 0x2000>,	// GICH
		      <0x0 0x2c02f000 0 0x2000>;	// GICV
		interrupts = <1 9 4>;

		its: its@2f020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <100000000>;
	};

	timer@2a810000 {
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x2a810000 0x0 0x10000>;
			clock-frequency = <100000000>;
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			frame@2a830000 {
				frame-number = <1>;
				interrupts = <0 26 4>;
				reg = <0x0 0x2a830000 0x0 0x10000>;
			};
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <0 60 4>,
			     <0 61 4>,
			     <0 62 4>,
			     <0 63 4>;
	};

	smb@0,0 {
		compatible = "simple-bus";

		#address-cells = <2>;
		#size-cells = <1>;
		ranges = <0 0 0 0x08000000 0x04000000>,
			 <1 0 0 0x14000000 0x04000000>,
			 <2 0 0 0x18000000 0x04000000>,
			 <3 0 0 0x1c000000 0x04000000>,
			 <4 0 0 0x0c000000 0x04000000>,
			 <5 0 0 0x10000000 0x04000000>;

		#include "rtsm_ve-motherboard.dtsi"
	};

	panels {
		panel {
			compatible	= "panel";
			mode		= "XVGA";
			refresh		= <60>;
			xres		= <1024>;
			yres		= <768>;
			pixclock	= <15748>;
			left_margin	= <152>;
			right_margin	= <48>;
			upper_margin	= <23>;
			lower_margin	= <3>;
			hsync_len	= <104>;
			vsync_len	= <4>;
			sync		= <0>;
			vmode		= "FB_VMODE_NONINTERLACED";
			tim2		= "TIM2_BCD", "TIM2_IPC";
			cntl		= "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
			caps		= "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
			bpp		= <16>;
		};
	};
};