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52 lines
1.5 KiB
52 lines
1.5 KiB
5 years ago
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <drivers/arm/scu.h>
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#include <lib/mmio.h>
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#include <plat/common/platform.h>
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#include <stdint.h>
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/*******************************************************************************
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* Turn ON snoop control unit. This is needed to synchronize the data between
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* CPU's.
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******************************************************************************/
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void enable_snoop_ctrl_unit(uintptr_t base)
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{
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uint32_t scu_ctrl;
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INFO("[SCU]: enabling snoop control unit ... \n");
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assert(base != 0U);
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scu_ctrl = mmio_read_32(base + SCU_CTRL_REG);
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/* already enabled? */
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if ((scu_ctrl & SCU_ENABLE_BIT) != 0) {
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return;
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}
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scu_ctrl |= SCU_ENABLE_BIT;
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mmio_write_32(base + SCU_CTRL_REG, scu_ctrl);
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}
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/*******************************************************************************
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* Snoop Control Unit configuration register. This is read-only register and
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* contains information such as
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* - number of CPUs present
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* - is a particular CPU operating in SMP mode or AMP mode
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* - data cache size of a particular CPU
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* - does SCU has ACP port
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* - is L2CPRESENT
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* NOTE: user of this API should interpert the bits in this register according
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* to the TRM
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******************************************************************************/
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uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base)
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{
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assert(base != 0U);
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return mmio_read_32(base + SCU_CFG_REG);
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}
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