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arm-trusted-firmware/plat/renesas/common/include/platform_def.h

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rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
6 years ago
/*
fix(rcar3-drivers): check loaded NS image area Check if next NS image invades a previous loaded image. Correct non secure image area to avoid loading a NS image to secure Move GZ compressed payload at 32 * compressed payload size offset, so it is loaded in non-secure area and can be decompressed into non-secure area too. It is unlikely that the up to 2 MiB compressed BL33 blob would decompress to payload larger than 64 MiB . Signed-off-by: Tobias Rist <tobias.rist@joynext.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> # Fix for compressed BL33 Change-Id: I52fd556aab50687e4791e5dbc45d425f802c8757
2 years ago
* Copyright (c) 2015-2023, Renesas Electronics Corporation. All rights reserved.
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
6 years ago
*
* SPDX-License-Identifier: BSD-3-Clause
*/
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
6 years ago
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
6 years ago
Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
5 years ago
#ifndef __ASSEMBLER__
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com> Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1" MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher <simon.butcher@arm.com> Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas' Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com> Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com> * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam <festevam@gmail.com> Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas' ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel's cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p "Switch off SW23 and press return " foo echo mem > /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 > /sys/devices/system/cpu/cpu$nbr/online printf "ONLINE: " && cat /sys/devices/system/cpu/online printf "OFFLINE: " && cat /sys/devices/system/cpu/offline Signed-off-by: ldts <jramirez@baylibre.com>
6 years ago
#include <stdlib.h>
#endif
Sanitise includes across codebase Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn&#39;t a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 (&#34;Fix gpio includes of mt8173 platform to avoid collision.&#34;). More recently, this patch has had similar problems: 46f9b2c3a282 (&#34;drivers: add tzc380 support&#34;). This problem was introduced in commit 4ecca33988b9 (&#34;Move include and source files to logical locations&#34;). At that time, there weren&#39;t too many headers so it wasn&#39;t a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz &lt;antonio.ninodiaz@arm.com&gt;
6 years ago
#include <arch.h>
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#include "rcar_def.h"
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
#define FIRMWARE_WELCOME_STR "Booting Rcar-gen3 Trusted Firmware\n"
/* Size of cacheable stacks */
#if IMAGE_BL1
#if TRUSTED_BOARD_BOOT
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define PLATFORM_STACK_SIZE U(0x1000)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#else
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define PLATFORM_STACK_SIZE U(0x440)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
#elif IMAGE_BL2
#if TRUSTED_BOARD_BOOT
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define PLATFORM_STACK_SIZE U(0x1000)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#else
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define PLATFORM_STACK_SIZE U(0x400)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
#elif IMAGE_BL31
fix(plat/rcar3): change stack size of BL31 Increase the stack size to avoid stack overflow when the LOG_LEVEL compile option is set high. Signed-off-by: Hideyuki Nitta &lt;hideyuki.nitta.jf@hitachi.com&gt; Signed-off-by: Toshiyuki Ogasahara &lt;toshiyuki.ogasahara.bo@hitachi.com&gt; Signed-off-by: Yoshifumi Hosoya &lt;yoshifumi.hosoya.wj@renesas.com&gt; Change-Id: I25047322763bff148dba13848a3a40f4c7cf90b7
3 years ago
#define PLATFORM_STACK_SIZE U(0x800)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#elif IMAGE_BL32
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define PLATFORM_STACK_SIZE U(0x440)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
#define BL332_IMAGE_ID (NS_BL2U_IMAGE_ID + 1)
#define BL333_IMAGE_ID (NS_BL2U_IMAGE_ID + 2)
#define BL334_IMAGE_ID (NS_BL2U_IMAGE_ID + 3)
#define BL335_IMAGE_ID (NS_BL2U_IMAGE_ID + 4)
#define BL336_IMAGE_ID (NS_BL2U_IMAGE_ID + 5)
#define BL337_IMAGE_ID (NS_BL2U_IMAGE_ID + 6)
#define BL338_IMAGE_ID (NS_BL2U_IMAGE_ID + 7)
#define BL332_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 8)
#define BL333_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 9)
#define BL334_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 10)
#define BL335_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 11)
#define BL336_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 12)
#define BL337_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 13)
#define BL338_KEY_CERT_ID (NS_BL2U_IMAGE_ID + 14)
#define BL332_CERT_ID (NS_BL2U_IMAGE_ID + 15)
#define BL333_CERT_ID (NS_BL2U_IMAGE_ID + 16)
#define BL334_CERT_ID (NS_BL2U_IMAGE_ID + 17)
#define BL335_CERT_ID (NS_BL2U_IMAGE_ID + 18)
#define BL336_CERT_ID (NS_BL2U_IMAGE_ID + 19)
#define BL337_CERT_ID (NS_BL2U_IMAGE_ID + 20)
#define BL338_CERT_ID (NS_BL2U_IMAGE_ID + 21)
/* io drivers id */
#define FLASH_DEV_ID U(0)
#define EMMC_DEV_ID U(1)
/*
* R-Car H3 Cortex-A57
* L1:I/48KB(16KBx3way) D/32KB(16KBx2way) L2:2MB(128KBx16way)
* Cortex-A53
* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
*/
rcar_gen3: plat: Fix cache line size The CPU has cache line size of 64 Bytes, fix the cache line size. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#define PLATFORM_CACHE_LINE_SIZE 64
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(2)
#define MAX_IO_DEVICES U(3)
#define MAX_IO_HANDLES U(4)
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
/*
******************************************************************************
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
* BL2 specific defines.
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
******************************************************************************
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#define RCAR_SYSRAM_BASE U(0xE6300000)
rcar_gen3: plat: Add initial D3 support Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
rcar_gen3: plat: Fix BL2 size check Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#define BL2_LIMIT U(0xE6320000)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#else
rcar_gen3: plat: Fix BL2 size check Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#define BL2_LIMIT U(0xE6360000)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
rcar_gen3: plat: Add initial D3 support Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RCAR_D3)
rcar_gen3: plat: Add R-Car V3M support Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov &lt;vladimir.barinov@cogentembedded.com&gt; Signed-off-by: Valentine Barshak &lt;valentine.barshak@cogentembedded.com&gt; Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt; --- Marek: Update on top of mainline ATF/master
6 years ago
#define BL2_BASE U(0xE6304000)
rcar_gen3: plat: Fix BL2 size check Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#define BL2_IMAGE_LIMIT U(0xE6318000)
rcar_gen3: plat: Add R-Car V3M support Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov &lt;vladimir.barinov@cogentembedded.com&gt; Signed-off-by: Valentine Barshak &lt;valentine.barshak@cogentembedded.com&gt; Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt; --- Marek: Update on top of mainline ATF/master
6 years ago
#elif (RCAR_LSI == RCAR_V3M)
#define BL2_BASE U(0xE6344000)
#define BL2_IMAGE_LIMIT U(0xE636E800)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#else
rcar_gen3: plat: Add R-Car V3M support Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov &lt;vladimir.barinov@cogentembedded.com&gt; Signed-off-by: Valentine Barshak &lt;valentine.barshak@cogentembedded.com&gt; Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt; --- Marek: Update on top of mainline ATF/master
6 years ago
#define BL2_BASE U(0xE6304000)
rcar_gen3: plat: Fix BL2 size check Rename BL2_LIMIT to BL2_IMAGE_LIMIT and BL2_SYSRAM_LIMIT to BL2_LIMIT to correctly set BL2_LIMIT value. Set correct DEVICE_SRAM_BASE to match the hardware. Use BL2_END in rcar_configure_mmu_el3() to mark the cacheable BL2 area. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
6 years ago
#define BL2_IMAGE_LIMIT U(0xE632E800)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
/*
******************************************************************************
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
* BL31 specific defines.
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
******************************************************************************
* Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
* current BL3-1 debug size plus a little space for growth.
*/
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#define BL31_BASE (RCAR_TRUSTED_SRAM_BASE)
#define BL31_LIMIT (RCAR_TRUSTED_SRAM_BASE + \
RCAR_TRUSTED_SRAM_SIZE)
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
#define RCAR_BL31_LOG_BASE (0x44040000)
#define RCAR_BL31_SDRAM_BTM (RCAR_BL31_LOG_BASE + 0x14000)
#define RCAR_BL31_LOG_SIZE (RCAR_BL31_SDRAM_BTM - RCAR_BL31_LOG_BASE)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#define BL31_SRAM_BASE (DEVICE_SRAM_BASE)
#define BL31_SRAM_LIMIT (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
/*******************************************************************************
* BL32 specific defines.
******************************************************************************/
#ifndef SPD_NONE
#define BL32_BASE U(0x44100000)
fix(rcar3-drivers): check loaded NS image area Check if next NS image invades a previous loaded image. Correct non secure image area to avoid loading a NS image to secure Move GZ compressed payload at 32 * compressed payload size offset, so it is loaded in non-secure area and can be decompressed into non-secure area too. It is unlikely that the up to 2 MiB compressed BL33 blob would decompress to payload larger than 64 MiB . Signed-off-by: Tobias Rist &lt;tobias.rist@joynext.com&gt; Signed-off-by: Yoshifumi Hosoya &lt;yoshifumi.hosoya.wj@renesas.com&gt; Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt; # Fix for compressed BL33 Change-Id: I52fd556aab50687e4791e5dbc45d425f802c8757
2 years ago
#define BL32_SIZE U(0x200000)
#define BL32_LIMIT (BL32_BASE + BL32_SIZE)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
#endif
/*******************************************************************************
* BL33
******************************************************************************/
#define BL33_BASE DRAM1_NS_BASE
feat(plat/rcar3): add optional support for gzip-compressed BL33 The BL33 size on this platform is limited to 1 MiB, add optional support for decompressing and starting gzip-compressed BL33, which may help with this size limitation. This functionality is disabled by default, set RCAR_GEN3_BL33_GZIP=1 during build to enable it. The BL33 at 0x50000000 should then be gzip compressed, however if the BL33 does not have a valid gzip header, it is copied to the correct location and started as-is, this is a fallback for legacy systems and systems which update to gzip-compressed BL33. Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt; Change-Id: Id93f1c7e6f17db1ffb952ea086562993473f6efa
4 years ago
#define BL33_COMP_SIZE U(0x200000)
fix(rcar3-drivers): check loaded NS image area Check if next NS image invades a previous loaded image. Correct non secure image area to avoid loading a NS image to secure Move GZ compressed payload at 32 * compressed payload size offset, so it is loaded in non-secure area and can be decompressed into non-secure area too. It is unlikely that the up to 2 MiB compressed BL33 blob would decompress to payload larger than 64 MiB . Signed-off-by: Tobias Rist &lt;tobias.rist@joynext.com&gt; Signed-off-by: Yoshifumi Hosoya &lt;yoshifumi.hosoya.wj@renesas.com&gt; Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@mailbox.org&gt; # Fix for compressed BL33 Change-Id: I52fd556aab50687e4791e5dbc45d425f802c8757
2 years ago
#define BL33_DECOMP_SIZE (BL33_COMP_SIZE * 32)
#define BL33_COMP_BASE (BL33_BASE + BL33_DECOMP_SIZE)
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#if IMAGE_BL1
#define MAX_XLAT_TABLES U(2)
#elif IMAGE_BL2
#define MAX_XLAT_TABLES U(5)
#elif IMAGE_BL31
#define MAX_XLAT_TABLES U(4)
#elif IMAGE_BL32
#define MAX_XLAT_TABLES U(3)
#endif
#if IMAGE_BL2
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 40)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 40)
#else
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
#endif
#define MAX_MMAP_REGIONS (RCAR_MMAP_ENTRIES + RCAR_BL_REGIONS)
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
plat: renesas: rcar: include: Code cleanup This patch fixes checkpatch warnings and replaces TAB with space after #define macros. Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt; Reviewed-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt; Change-Id: I11f65d494997cbf612376fb120c27ef0166cdd3a
4 years ago
* caches. Such alignment ensures that two mailboxes do not sit on the same cache
rcar-gen3: initial commit for the rcar-gen3 boards Reference code: ============== rar_gen3: IPL and Secure Monitor Rev1.0.22 https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3] Author: Takuya Sakata &lt;takuya.sakata.wz@bp.renesas.com&gt; Date: Thu Aug 30 21:26:41 2018 +0900 Update IPL and Secure Monitor Rev1.0.22 General Information: =================== This port has been tested on the Salvator-X Soc_id r8a7795 revision ES1.1 (uses an SPD). Build Tested: ------------- ATFW_OPT=&#34;LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1&#34; MBEDTLS_DIR=$mbedtls $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed Other dependencies: ------------------ * mbed_tls: git@github.com:ARMmbed/mbedtls.git [devel] Merge: 68dbc94 f34a4c1 Author: Simon Butcher &lt;simon.butcher@arm.com&gt; Date: Thu Aug 30 00:57:28 2018 +0100 * optee_os: https://github.com/BayLibre/optee_os Until it gets merged into OP-TEE, the port requires Renesas&#39; Trusted Environment with a modification to support power management. Author: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; Date: Thu Aug 30 16:49:49 2018 +0200 plat-rcar: cpu-suspend: handle the power level Signed-off-by: Jorge Ramirez-Ortiz &lt;jramirez@baylibre.com&gt; * u-boot: The port has beent tested using mainline uboot. Author: Fabio Estevam &lt;festevam@gmail.com&gt; Date: Tue Sep 4 10:23:12 2018 -0300 *linux: The port has beent tested using mainline kernel. Author: Linus Torvalds &lt;torvalds@linux-foundation.org&gt; Date: Sun Sep 16 11:52:37 2018 -0700 Linux 4.19-rc4 Overview --------- BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered at this exception level (the Renesas&#39; ATF reference tree [1] resets into EL1 before entering BL2 - see its bl2.ld.S) BL2 initializes DDR (and i2c to talk to the PMIC on some platforms) before determining the boot reason (cold or warm). During suspend all CPUs are switched off and the DDR is put in backup mode (some kind of self-refresh mode). This means that BL2 is always entered in a cold boot scenario. Once BL2 boots, it determines the boot reason, writes it to shared memory (BOOT_KIND_BASE) together with the BL31 parameters (PARAMS_BASE) and jumps to BL31. To all effects, BL31 is as if it is being entered in reset mode since it still needs to initialize the rest of the cores; this is the reason behind using direct shared memory access to BOOT_KIND_BASE and PARAMS_BASE instead of using registers to get to those locations (see el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use case). Depending on the boot reason BL31 initializes the rest of the cores: in case of suspend, it uses a MBOX memory region to recover the program counters. [1] https://github.com/renesas-rcar/arm-trusted-firmware Tests ----- * cpuidle ------- enable kernel&#39;s cpuidle arm_idle driver and boot * system suspend -------------- $ cat suspend.sh #!/bin/bash i2cset -f -y 7 0x30 0x20 0x0F read -p &#34;Switch off SW23 and press return &#34; foo echo mem &gt; /sys/power/state * cpu hotplug: ------------ $ cat offline.sh #!/bin/bash nbr=$1 echo 0 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline $ cat online.sh #!/bin/bash nbr=$1 echo 1 &gt; /sys/devices/system/cpu/cpu$nbr/online printf &#34;ONLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/online printf &#34;OFFLINE: &#34; &amp;&amp; cat /sys/devices/system/cpu/offline Signed-off-by: ldts &lt;jramirez@baylibre.com&gt;
6 years ago
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT (6)
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/*******************************************************************************
* Size of the per-cpu data in bytes that should be reserved in the generic
* per-cpu data structure for the RCAR port.
******************************************************************************/
#if !USE_COHERENT_MEM
#define PLAT_PCPU_DATA_SIZE (2)
#endif
Standardise header guards across codebase All identifiers, regardless of use, that start with two underscores are reserved. This means they can&#39;t be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by &#39;H&#39;. For example, for a file called &#34;uart_example.h&#34;, the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz &lt;antonio.ninodiaz@arm.com&gt;
6 years ago
#endif /* PLATFORM_DEF_H */