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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RK3288_DEF_H
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#define RK3288_DEF_H
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/* Special value used to verify platform parameters from BL2 to BL31 */
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#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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#define SIZE_K(n) ((n) * 1024)
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#define SIZE_M(n) ((n) * 1024 * 1024)
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#define SRAM_TEXT_LIMIT (4 * 1024)
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#define SRAM_DATA_LIMIT (4 * 1024)
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#define DDR_PCTL0_BASE 0xff610000
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#define DDR_PCTL0_SIZE SIZE_K(64)
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#define DDR_PHY0_BASE 0xff620000
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#define DDR_PHY0_SIZE SIZE_K(64)
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#define DDR_PCTL1_BASE 0xff630000
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#define DDR_PCTL1_SIZE SIZE_K(64)
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#define DDR_PHY1_BASE 0xff640000
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#define DDR_PHY1_SIZE SIZE_K(64)
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#define UART0_BASE 0xff180000
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#define UART0_SIZE SIZE_K(64)
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#define UART1_BASE 0xff190000
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#define UART1_SIZE SIZE_K(64)
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#define UART2_BASE 0xff690000
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#define UART2_SIZE SIZE_K(64)
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#define UART3_BASE 0xff1b0000
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#define UART3_SIZE SIZE_K(64)
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#define UART4_BASE 0xff1c0000
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#define UART4_SIZE SIZE_K(64)
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/* 96k instead of 64k? */
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#define SRAM_BASE 0xff700000
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#define SRAM_SIZE SIZE_K(64)
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#define PMUSRAM_BASE 0xff720000
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#define PMUSRAM_SIZE SIZE_K(4)
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#define PMUSRAM_RSIZE SIZE_K(4)
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#define PMU_BASE 0xff730000
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#define PMU_SIZE SIZE_K(64)
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#define SGRF_BASE 0xff740000
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#define SGRF_SIZE SIZE_K(64)
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#define CRU_BASE 0xff760000
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#define CRU_SIZE SIZE_K(64)
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#define GRF_BASE 0xff770000
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#define GRF_SIZE SIZE_K(64)
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/* timer 6+7 can be set as secure in SGRF */
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#define STIME_BASE 0xff810000
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#define STIME_SIZE SIZE_K(64)
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#define SERVICE_BUS_BASE 0xffac0000
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#define SERVICE_BUS_SIZE SIZE_K(64)
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#define TZPC_BASE 0xffb00000
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#define TZPC_SIZE SIZE_K(64)
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#define GIC400_BASE 0xffc00000
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#define GIC400_SIZE SIZE_K(64)
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#define CORE_AXI_BUS_BASE 0xffd00000
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#define CORE_AXI_BUS_SIZE SIZE_M(1)
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#define COLD_BOOT_BASE 0xffff0000
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/**************************************************************************
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* UART related constants
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**************************************************************************/
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#define RK3288_BAUDRATE 115200
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#define RK3288_UART_CLOCK 24000000
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/******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_TICKS 24000000
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/******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* Base rk_platform compatible GIC memory map */
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#define RK3288_GICD_BASE (GIC400_BASE + 0x1000)
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#define RK3288_GICC_BASE (GIC400_BASE + 0x2000)
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#define RK3288_GICR_BASE 0 /* no GICR in GIC-400 */
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/******************************************************************************
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* sgi, ppi
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******************************************************************************/
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#define RK_IRQ_SEC_PHY_TIMER 29
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/* what are these, and are they present on rk3288? */
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#define RK_IRQ_SEC_SGI_0 8
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#define RK_IRQ_SEC_SGI_1 9
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#define RK_IRQ_SEC_SGI_2 10
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#define RK_IRQ_SEC_SGI_3 11
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#define RK_IRQ_SEC_SGI_4 12
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#define RK_IRQ_SEC_SGI_5 13
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#define RK_IRQ_SEC_SGI_6 14
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#define RK_IRQ_SEC_SGI_7 15
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/*
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* Define a list of Group 0 interrupts.
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*/
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#define PLAT_RK_GICV2_G0_IRQS \
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INTR_PROP_DESC(RK_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(RK_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
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#endif /* RK3288_DEF_H */
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