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/*
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* Copyright (C) 2017 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef ARO_H
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#define ARO_H
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enum hws_freq {
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CPU_FREQ_2000,
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CPU_FREQ_1800,
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CPU_FREQ_1600,
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CPU_FREQ_1400,
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CPU_FREQ_1300,
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CPU_FREQ_1200,
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CPU_FREQ_1000,
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CPU_FREQ_600,
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CPU_FREQ_800,
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DDR_FREQ_LAST,
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DDR_FREQ_SAR
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};
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#include <mvebu_def.h>
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enum cpu_clock_freq_mode {
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CPU_2000_DDR_1200_RCLK_1200 = 0x0,
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CPU_2000_DDR_1050_RCLK_1050 = 0x1,
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CPU_1600_DDR_800_RCLK_800 = 0x4,
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CPU_2200_DDR_1200_RCLK_1200 = 0x6,
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CPU_1800_DDR_1050_RCLK_1050 = 0x7,
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CPU_1600_DDR_900_RCLK_900 = 0x0B,
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CPU_1600_DDR_1050_RCLK_1050 = 0x0D,
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CPU_1600_DDR_1200_RCLK_1200 = 0x0D,
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CPU_1600_DDR_900_RCLK_900_2 = 0x0E,
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CPU_1000_DDR_650_RCLK_650 = 0x13,
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CPU_1300_DDR_800_RCLK_800 = 0x14,
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CPU_1300_DDR_650_RCLK_650 = 0x17,
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CPU_1200_DDR_800_RCLK_800 = 0x19,
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CPU_1400_DDR_800_RCLK_800 = 0x1a,
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CPU_600_DDR_800_RCLK_800 = 0x1B,
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CPU_800_DDR_800_RCLK_800 = 0x1C,
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CPU_1000_DDR_800_RCLK_800 = 0x1D,
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CPU_DDR_RCLK_INVALID
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};
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int init_aro(void);
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#endif /* ARO_H */
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