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arm-trusted-firmware/plat/xilinx/zynqmp/platform.mk

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Fix incorrect copyright notices Some files have incorrect copyright notices, this patch fixes all files with deviations from the standard notice. Change-Id: I66b73e78a50a235acb55f1e2ec2052a42c0570d2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
8 years ago
#
Move plat/common source file definitions to generic Makefiles These source file definitions should be defined in generic Makefiles so that all platforms can benefit. Ensure that the symbols are properly marked as weak so they can be overridden by platforms. NOTE: This change is a potential compatibility break for non-upstream platforms. Change-Id: I7b892efa9f2d6d216931360dc6c436e1d10cffed Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
8 years ago
# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
#
Use SPDX license identifiers To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
8 years ago
# SPDX-License-Identifier: BSD-3-Clause
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
zynqmp: Enable workaround for errata 855873 Zynqmp implements a version of the Cortex A53 affected by errata 855873. Enable the workaround for the errata and silence the warning: "WARNING: BL31: cortex_a53: errata workaround for 855873 was missing!". Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
8 years ago
override ERRATA_A53_855873 := 1
zynqmp: add "override" directive to mandatory options The platform.mk sets build options required for ZynqMP, but users can still change them from the command line, like: make PLAT=zynqmp RESET_TO_BL31=0 CROSS_COMPILE=... Then, the makefile shows an error message in that case: Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1. If the option is not user-configurable, the makefile can specify "override" to prevent users from changing it. We do not need the error message for the case that never happens. Likewise, ENABLE_PLAT_COMPAT := 0 and PROGRAMMABLE_RESET_ADDRESS := 1 are mandatory to avoid build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
8 years ago
override ENABLE_PLAT_COMPAT := 0
override PROGRAMMABLE_RESET_ADDRESS := 1
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
PSCI_EXTENDED_STATE_ID := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
zynqmp: Separate code and rodata Set the SEPARATE_CODE_AND_RODATA build flag to map read-only data as execute never. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
8 years ago
SEPARATE_CODE_AND_RODATA := 1
zynqmp: add "override" directive to mandatory options The platform.mk sets build options required for ZynqMP, but users can still change them from the command line, like: make PLAT=zynqmp RESET_TO_BL31=0 CROSS_COMPILE=... Then, the makefile shows an error message in that case: Using BL31 as the reset vector is only one option supported on ZynqMP. Please set RESET_TO_BL31 to 1. If the option is not user-configurable, the makefile can specify "override" to prevent users from changing it. We do not need the error message for the case that never happens. Likewise, ENABLE_PLAT_COMPAT := 0 and PROGRAMMABLE_RESET_ADDRESS := 1 are mandatory to avoid build error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
8 years ago
override RESET_TO_BL31 := 1
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
zynqmp: Revise memory configuration options Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
9 years ago
ifdef ZYNQMP_ATF_MEM_BASE
$(eval $(call add_define,ZYNQMP_ATF_MEM_BASE))
ifndef ZYNQMP_ATF_MEM_SIZE
$(error "ZYNQMP_ATF_BASE defined without ZYNQMP_ATF_SIZE")
endif
$(eval $(call add_define,ZYNQMP_ATF_MEM_SIZE))
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
zynqmp: Revise memory configuration options Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
9 years ago
ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE
$(eval $(call add_define,ZYNQMP_ATF_MEM_PROGBITS_SIZE))
endif
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
endif
zynqmp: Revise memory configuration options Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
9 years ago
ifdef ZYNQMP_BL32_MEM_BASE
$(eval $(call add_define,ZYNQMP_BL32_MEM_BASE))
ifndef ZYNQMP_BL32_MEM_SIZE
$(error "ZYNQMP_BL32_BASE defined without ZYNQMP_BL32_SIZE")
endif
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
zynqmp: Add option to select between Cadence UARTs Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd UART available in the SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
9 years ago
ZYNQMP_CONSOLE ?= cadence
$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iinclude/plat/arm/common/aarch64/ \
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/
Migrate platform ports to the new xlat_tables library This patch modifies the upstream platform port makefiles to use the new xlat_tables library files. This patch also makes mmap region setup common between AArch64 and AArch32 for FVP platform port. The file `fvp_common.c` is moved from the `plat/arm/board/fvp/aarch64` folder to the parent folder as it is not specific to AArch64. Change-Id: Id2e9aac45e46227b6f83cccfd1e915404018ea0b
9 years ago
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
zynqmp: Add support for generic_delay_timer Initialize the generic_delay_timer in the zynqmp port. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
Migrate platform makefile to new console driver location This patch migrates the upstream platform makefiles to include the console drivers from the new location in ARM Trusted Firmware code base. Change-Id: I866d6c4951e475de1f836ce8a8c1d5e6da9577e3
8 years ago
drivers/cadence/uart/aarch64/cdns_console.S \
drivers/console/aarch64/console.S \
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
plat/arm/common/aarch64/arm_helpers.S \
plat/arm/common/arm_cci.c \
Move `arm_common.c` out of aarch64 folder This patch moves the `arm_common.c` file from `plat/arm/common/aarch64/` to the parent directory since the functions implemented in the file are not AArch64 specific. The platform makefiles are also modified for this change. Change-Id: I776d2e4958f59041476cf2f53a9adb5b2d304ee0
8 years ago
plat/arm/common/arm_common.c \
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
plat/arm/common/arm_gicv2.c \
plat/common/plat_gicv2.c \
plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
Include `plat_psci_common.c` from the new location The `plat_psci_common.c` was moved to the new location `plat/common` and a stub file was retained at previous location for compatibility. This patch modifies the platform makefiles to include the file from the new location. Change-Id: Iabddeeb824e9a5d72d176d7c644735966c8c0699
9 years ago
plat/common/plat_psci_common.c \
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
plat/xilinx/zynqmp/bl31_zynqmp_setup.c \
plat/xilinx/zynqmp/plat_psci.c \
plat/xilinx/zynqmp/plat_zynqmp.c \
zynqmp: FSBL->ATF handover Parse the parameter structure the FSBL populates, to populate the bl32 and bl33 image structures. Cc: Sarat Chand Savitala <saratcha@xilinx.com> Cc: petalinux-dev@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> [ SB - pass pointers to structs instead of structs - handle execution state parameter - populate bl32 SPSR - add documentation - query bootmode and consider missing handoff parameters an error when not in JTAG boot mode ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
10 years ago
plat/xilinx/zynqmp/plat_startup.c \
Add support for Xilinx Zynq UltraScale+ MPSOC The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
9 years ago
plat/xilinx/zynqmp/plat_topology.c \
plat/xilinx/zynqmp/sip_svc_setup.c \
plat/xilinx/zynqmp/pm_service/pm_svc_main.c \
plat/xilinx/zynqmp/pm_service/pm_api_sys.c \
plat/xilinx/zynqmp/pm_service/pm_ipi.c \
plat/xilinx/zynqmp/pm_service/pm_client.c