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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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.globl bl2u_vector_table
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.globl bl2u_entrypoint
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vector_base bl2u_vector_table
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b bl2u_entrypoint
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b report_exception /* Undef */
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b report_exception /* SVC call */
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b report_exception /* Prefetch abort */
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b report_exception /* Data abort */
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b report_exception /* Reserved */
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b report_exception /* IRQ */
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b report_exception /* FIQ */
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func bl2u_entrypoint
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/*---------------------------------------------
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* Save from r1 the extents of the trusted ram
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* available to BL2U for future use.
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* r0 is not currently used.
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* ---------------------------------------------
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*/
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mov r11, r1
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mov r10, r2
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/* ---------------------------------------------
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* Set the exception vector to something sane.
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* ---------------------------------------------
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*/
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ldr r0, =bl2u_vector_table
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stcopr r0, VBAR
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isb
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/* --------------------------------------------------------
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* Enable the instruction cache - disable speculative loads
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* --------------------------------------------------------
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*/
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ldcopr r0, SCTLR
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orr r0, r0, #SCTLR_I_BIT
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bic r0, r0, #SCTLR_DSSBS_BIT
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stcopr r0, SCTLR
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isb
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/* ---------------------------------------------
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* Since BL2U executes after BL1, it is assumed
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* here that BL1 has already has done the
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* necessary register initializations.
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* ---------------------------------------------
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*/
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/* ---------------------------------------------
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* Invalidate the RW memory used by the BL2U
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* image. This includes the data and NOBITS
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* sections. This is done to safeguard against
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* possible corruption of this memory by dirty
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* cache lines in a system cache as a result of
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* use by an earlier boot loader stage.
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* ---------------------------------------------
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*/
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ldr r0, =__RW_START__
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ldr r1, =__RW_END__
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sub r1, r1, r0
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bl inv_dcache_range
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/* ---------------------------------------------
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* Zero out NOBITS sections. There are 2 of them:
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* - the .bss section;
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* - the coherent memory section.
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* ---------------------------------------------
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*/
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ldr r0, =__BSS_START__
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ldr r1, =__BSS_SIZE__
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bl zeromem
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/* --------------------------------------------
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* Allocate a stack whose memory will be marked
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* as Normal-IS-WBWA when the MMU is enabled.
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* There is no risk of reading stale stack
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* memory after enabling the MMU as only the
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* primary cpu is running at the moment.
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* --------------------------------------------
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*/
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bl plat_set_my_stack
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/* ---------------------------------------------
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* Initialize the stack protector canary before
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* any C code is called.
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* ---------------------------------------------
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*/
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#if STACK_PROTECTOR_ENABLED
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bl update_stack_protector_canary
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#endif
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/* ---------------------------------------------
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* Perform early platform setup & platform
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* specific early arch. setup e.g. mmu setup
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* ---------------------------------------------
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*/
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mov r0, r11
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mov r1, r10
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bl bl2u_early_platform_setup
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bl bl2u_plat_arch_setup
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/* ---------------------------------------------
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* Jump to main function.
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* ---------------------------------------------
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*/
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bl bl2u_main
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/* ---------------------------------------------
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* Should never reach this point.
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* ---------------------------------------------
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*/
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no_ret plat_panic_handler
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endfunc bl2u_entrypoint
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