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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef SECURE_H
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#define SECURE_H
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/**************************************************
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* sgrf reg, offset
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**************************************************/
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#define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4)
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#define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4)
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#define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4)
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#define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\
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(n < 8 ? SGRF_SOC_CON3_7(n) :\
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SGRF_SOC_CON8_15(n)))
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#define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4)
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#define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4)
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#define SGRF_DDRRGN_CON0_16(n) ((n) * 4)
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#define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4)
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/* All of master in ns */
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#define SGRF_SOC_ALLMST_NS 0xffff
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/* security config for slave */
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#define SGRF_SLV_S_WMSK 0xffff0000
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#define SGRF_SLV_S_ALL_NS 0x0
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/* security config pmu slave ip */
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/* All of slaves is ns */
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#define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0)
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/* slaves secure attr is configed */
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#define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0)
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#define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1)
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#define SGRF_PMUSRAM_S BIT(8)
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#define SGRF_INTSRAM_S BIT(13)
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/* ddr region */
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#define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */
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#define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */
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#define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */
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/* All security of the DDR RGNs are bypass */
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#define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9)
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/* All security of the DDR RGNs are not bypass */
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#define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9)
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/* The MST access the ddr rgn n with secure attribution */
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#define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n))
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/* bits[16:8]*/
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#define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8)
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#define SGRF_PMU_CON0 0x0c100
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#define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4)
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/**************************************************
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* secure timer
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**************************************************/
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/* chanal0~5 */
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#define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n))
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/* chanal6~11 */
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#define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n))
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/* low 32 bits */
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#define TIMER_END_COUNT0 0x00
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/* high 32 bits */
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#define TIMER_END_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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/* low 32 bits */
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#define TIMER_INIT_COUNT0 0x10
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/* high 32 bits */
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#define TIMER_INIT_COUNT1 0x14
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#define TIMER_INTSTATUS 0x18
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#define TIMER_CONTROL_REG 0x1c
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#define TIMER_EN 0x1
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#define TIMER_FMODE (0x0 << 1)
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#define TIMER_RMODE (0x1 << 1)
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/**************************************************
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* secure WDT
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**************************************************/
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#define PCLK_WDT_CA53_GATE_SHIFT 8
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#define PCLK_WDT_CM0_GATE_SHIFT 10
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/* export secure operating APIs */
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void secure_watchdog_gate(void);
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__pmusramfunc void secure_watchdog_ungate(void);
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void secure_timer_init(void);
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void secure_sgrf_init(void);
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void secure_sgrf_ddr_rgn_init(void);
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__pmusramfunc void sram_secure_timer_init(void);
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#endif /* SECURE_H */
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