From 018b84803d3766c0733e50dc514d5f4ffce77cca Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Thu, 12 May 2016 13:43:33 -0700 Subject: [PATCH] Tegra: enable ECC/Parity protection for Cortex-A57 CPUs This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs for Tegra SoCs. Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9 Signed-off-by: Varun Wadekar --- docs/plat/nvidia-tegra.md | 7 +++++ include/lib/cpus/aarch64/cortex_a57.h | 2 ++ .../tegra/common/aarch64/tegra_helpers.S | 30 ++++++++++++++++--- 3 files changed, 35 insertions(+), 4 deletions(-) diff --git a/docs/plat/nvidia-tegra.md b/docs/plat/nvidia-tegra.md index f82085b13..b45fec6e5 100644 --- a/docs/plat/nvidia-tegra.md +++ b/docs/plat/nvidia-tegra.md @@ -84,3 +84,10 @@ The PSCI implementation expects each platform to expose the 'power state' parameter to be used during the 'SYSTEM SUSPEND' call. The state-id field is implementation defined on Tegra SoCs and is preferably defined by tegra_def.h. + +Tegra configs +============= + +* 'tegra_enable_l2_ecc_parity_prot': This flag enables the L2 ECC and Parity + Protection bit, for ARM Cortex-A57 CPUs, during CPU boot. This flag will + be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit. diff --git a/include/lib/cpus/aarch64/cortex_a57.h b/include/lib/cpus/aarch64/cortex_a57.h index c5a218b72..9229a564e 100644 --- a/include/lib/cpus/aarch64/cortex_a57.h +++ b/include/lib/cpus/aarch64/cortex_a57.h @@ -87,6 +87,8 @@ #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 +#define L2_ECC_PARITY_PROTECTION_BIT (1 << 21) + /******************************************************************************* * L2 Extended Control register specific definitions. ******************************************************************************/ diff --git a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S index a57d1cb0a..70a7f3a9b 100644 --- a/plat/nvidia/tegra/common/aarch64/tegra_helpers.S +++ b/plat/nvidia/tegra/common/aarch64/tegra_helpers.S @@ -68,6 +68,7 @@ .globl ns_image_entrypoint .globl tegra_bl31_phys_base .globl tegra_console_base + .globl tegra_enable_l2_ecc_parity_prot /* --------------------- * Common CPU init code @@ -76,8 +77,8 @@ .macro cpu_init_common /* ------------------------------------------------ - * We enable procesor retention and L2/CPUECTLR NS - * access for A57 CPUs only. + * We enable procesor retention, L2/CPUECTLR NS + * access and ECC/Parity protection for A57 CPUs * ------------------------------------------------ */ mrs x0, midr_el1 @@ -90,7 +91,7 @@ /* --------------------------- * Enable processor retention * --------------------------- - */ + */ mrs x0, L2ECTLR_EL1 mov x1, #RETENTION_ENTRY_TICKS_512 << L2ECTLR_RET_CTRL_SHIFT bic x0, x0, #L2ECTLR_RET_CTRL_MASK @@ -108,12 +109,26 @@ /* ------------------------------------------------------- * Enable L2 and CPU ECTLR RW access from non-secure world * ------------------------------------------------------- - */ + */ mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS msr actlr_el3, x0 msr actlr_el2, x0 isb + /* ------------------------------------------------------- + * Enable L2 ECC and Parity Protection + * ------------------------------------------------------- + */ + adr x0, tegra_enable_l2_ecc_parity_prot + ldr x0, [x0] + cbz x0, 1f + mrs x0, L2CTLR_EL1 + and x1, x0, #L2_ECC_PARITY_PROTECTION_BIT + cbnz x1, 1f + orr x0, x0, #L2_ECC_PARITY_PROTECTION_BIT + msr L2CTLR_EL1, x0 + isb + /* -------------------------------- * Enable the cycle count register * -------------------------------- @@ -454,3 +469,10 @@ tegra_bl31_phys_base: */ tegra_console_base: .quad 0 + + /* -------------------------------------------------- + * Enable L2 ECC and Parity Protection + * -------------------------------------------------- + */ +tegra_enable_l2_ecc_parity_prot: + .quad 0