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* changes: mmc: stm32_sdmmc2: correctly manage block size mmc: stm32_sdmmc2: manage max-frequency property from DT stm32mp1: move check_header() to common code stm32mp1: keep console during runtime stm32mp1: sp_min: initialize MMU and cache earlier stm32mp1: add support for LpDDR3 stm32mp1: use a common function to check spinlock is available clk: stm32mp: enable RTCAPB clock for dual-core chips stm32mp1: check if the SoC is single core stm32mp1: print information about board stm32mp1: print information about SoC stm32mp1: add watchdog supportpull/1934/head
Soby Mathew
5 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
18 changed files with 791 additions and 87 deletions
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/*
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* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <assert.h> |
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#include <errno.h> |
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#include <string.h> |
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#include <libfdt.h> |
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#include <platform_def.h> |
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#include <arch_helpers.h> |
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#include <common/debug.h> |
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#include <drivers/arm/gicv2.h> |
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#include <drivers/delay_timer.h> |
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#include <drivers/st/stm32_iwdg.h> |
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#include <drivers/st/stm32mp_clkfunc.h> |
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#include <lib/mmio.h> |
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#include <lib/utils.h> |
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#include <plat/common/platform.h> |
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/* IWDG registers offsets */ |
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#define IWDG_KR_OFFSET 0x00U |
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/* Registers values */ |
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#define IWDG_KR_RELOAD_KEY 0xAAAA |
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struct stm32_iwdg_instance { |
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uintptr_t base; |
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unsigned long clock; |
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uint8_t flags; |
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int num_irq; |
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}; |
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static struct stm32_iwdg_instance stm32_iwdg[IWDG_MAX_INSTANCE]; |
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static int stm32_iwdg_get_dt_node(struct dt_node_info *info, int offset) |
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{ |
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int node; |
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node = dt_get_node(info, offset, DT_IWDG_COMPAT); |
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if (node < 0) { |
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if (offset == -1) { |
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VERBOSE("%s: No IDWG found\n", __func__); |
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} |
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return -FDT_ERR_NOTFOUND; |
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} |
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return node; |
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} |
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void stm32_iwdg_refresh(void) |
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{ |
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uint8_t i; |
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for (i = 0U; i < IWDG_MAX_INSTANCE; i++) { |
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struct stm32_iwdg_instance *iwdg = &stm32_iwdg[i]; |
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/* 0x00000000 is not a valid address for IWDG peripherals */ |
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if (iwdg->base != 0U) { |
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stm32mp_clk_enable(iwdg->clock); |
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mmio_write_32(iwdg->base + IWDG_KR_OFFSET, |
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IWDG_KR_RELOAD_KEY); |
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stm32mp_clk_disable(iwdg->clock); |
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} |
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} |
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} |
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int stm32_iwdg_init(void) |
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{ |
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int node = -1; |
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struct dt_node_info dt_info; |
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void *fdt; |
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uint32_t __unused count = 0; |
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if (fdt_get_address(&fdt) == 0) { |
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panic(); |
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} |
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for (node = stm32_iwdg_get_dt_node(&dt_info, node); |
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node != -FDT_ERR_NOTFOUND; |
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node = stm32_iwdg_get_dt_node(&dt_info, node)) { |
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struct stm32_iwdg_instance *iwdg; |
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uint32_t hw_init; |
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uint32_t idx; |
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count++; |
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idx = stm32_iwdg_get_instance(dt_info.base); |
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iwdg = &stm32_iwdg[idx]; |
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iwdg->base = dt_info.base; |
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iwdg->clock = (unsigned long)dt_info.clock; |
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/* DT can specify low power cases */ |
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if (fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL) == |
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NULL) { |
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iwdg->flags |= IWDG_DISABLE_ON_STOP; |
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} |
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if (fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL) == |
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NULL) { |
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iwdg->flags |= IWDG_DISABLE_ON_STANDBY; |
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} |
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/* Explicit list of supported bit flags */ |
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hw_init = stm32_iwdg_get_otp_config(idx); |
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if ((hw_init & IWDG_HW_ENABLED) != 0) { |
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if (dt_info.status == DT_DISABLED) { |
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ERROR("OTP enabled but iwdg%u DT-disabled\n", |
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idx + 1U); |
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panic(); |
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} |
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iwdg->flags |= IWDG_HW_ENABLED; |
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} |
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if (dt_info.status == DT_DISABLED) { |
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zeromem((void *)iwdg, |
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sizeof(struct stm32_iwdg_instance)); |
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continue; |
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} |
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if ((hw_init & IWDG_DISABLE_ON_STOP) != 0) { |
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iwdg->flags |= IWDG_DISABLE_ON_STOP; |
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} |
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if ((hw_init & IWDG_DISABLE_ON_STANDBY) != 0) { |
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iwdg->flags |= IWDG_DISABLE_ON_STANDBY; |
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} |
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VERBOSE("IWDG%u found, %ssecure\n", idx + 1U, |
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((dt_info.status & DT_NON_SECURE) != 0) ? |
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"non-" : ""); |
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#if defined(IMAGE_BL2) |
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if (stm32_iwdg_shadow_update(idx, iwdg->flags) != BSEC_OK) { |
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return -1; |
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} |
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#endif |
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} |
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VERBOSE("%u IWDG instance%s found\n", count, (count > 1U) ? "s" : ""); |
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return 0; |
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} |
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@ -0,0 +1,19 @@ |
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/*
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* Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef STM32_IWDG_H |
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#define STM32_IWDG_H |
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#include <stdint.h> |
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#define IWDG_HW_ENABLED BIT(0) |
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#define IWDG_DISABLE_ON_STOP BIT(1) |
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#define IWDG_DISABLE_ON_STANDBY BIT(2) |
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int stm32_iwdg_init(void); |
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void stm32_iwdg_refresh(void); |
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#endif /* STM32_IWDG_H */ |
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/*
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* Copyright (c) 2015-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef STM32MP1_DBGMCU_H |
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#define STM32MP1_DBGMCU_H |
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#include <stdint.h> |
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/* Get chip version and ID from DBGMCU registers */ |
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int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version); |
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int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id); |
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/*
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* Freeze watchdog when a debugger is attached, if the security configuration |
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* allows it. |
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* Return 0 on success, a negative error value otherwise. |
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*/ |
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int stm32mp1_dbgmcu_freeze_iwdg2(void); |
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#endif /* STM32MP1_DBGMCU_H */ |
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@ -0,0 +1,96 @@ |
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/*
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* Copyright (c) 2016-2019, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <errno.h> |
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#include <platform_def.h> |
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#include <common/debug.h> |
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#include <drivers/st/bsec.h> |
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#include <drivers/st/stm32mp1_rcc.h> |
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#include <lib/mmio.h> |
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#include <lib/utils_def.h> |
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#include <stm32mp1_dbgmcu.h> |
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#define DBGMCU_IDC U(0x00) |
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#define DBGMCU_APB4FZ1 U(0x2C) |
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#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) |
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#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) |
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#define DBGMCU_IDC_REV_ID_SHIFT 16 |
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#define DBGMCU_APB4FZ1_IWDG2 BIT(2) |
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static uintptr_t get_rcc_base(void) |
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{ |
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/* This is called before stm32mp_rcc_base() is available */ |
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return RCC_BASE; |
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} |
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static int stm32mp1_dbgmcu_init(void) |
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{ |
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uint32_t dbg_conf; |
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uintptr_t rcc_base = get_rcc_base(); |
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dbg_conf = bsec_read_debug_conf(); |
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if ((dbg_conf & BSEC_DBGSWGEN) == 0U) { |
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uint32_t result = bsec_write_debug_conf(dbg_conf | |
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BSEC_DBGSWGEN); |
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if (result != BSEC_OK) { |
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ERROR("Error enabling DBGSWGEN\n"); |
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return -1; |
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} |
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} |
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mmio_setbits_32(rcc_base + RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); |
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return 0; |
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} |
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int stm32mp1_dbgmcu_get_chip_version(uint32_t *chip_version) |
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{ |
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if (stm32mp1_dbgmcu_init() != 0) { |
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return -EPERM; |
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} |
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*chip_version = (mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & |
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DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; |
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return 0; |
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} |
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int stm32mp1_dbgmcu_get_chip_dev_id(uint32_t *chip_dev_id) |
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{ |
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if (stm32mp1_dbgmcu_init() != 0) { |
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return -EPERM; |
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} |
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*chip_dev_id = mmio_read_32(DBGMCU_BASE + DBGMCU_IDC) & |
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DBGMCU_IDC_DEV_ID_MASK; |
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return 0; |
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} |
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int stm32mp1_dbgmcu_freeze_iwdg2(void) |
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{ |
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uint32_t dbg_conf; |
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if (stm32mp1_dbgmcu_init() != 0) { |
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return -EPERM; |
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} |
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dbg_conf = bsec_read_debug_conf(); |
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if ((dbg_conf & (BSEC_SPIDEN | BSEC_SPINDEN)) != 0U) { |
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mmio_setbits_32(DBGMCU_BASE + DBGMCU_APB4FZ1, |
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DBGMCU_APB4FZ1_IWDG2); |
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} |
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return 0; |
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} |
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