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This patch adds the essential AArch32 architecture helpers arch.h and arch_helpers.h and modifies `_types.h` to add AArch32 support. A new build option `ARCH` is defined in the top level makefile to enable the component makefiles to choose the right files based on the Architecture it is being build for. Depending on this flag, either `AARCH32` or `AARCH64` flag is defined by the Makefile. The default value of `ARCH` flag is `aarch64`. The AArch32 build support will be added in a later patch. Change-Id: I405e5fac02db828a55cd25989b572b64cb005241pull/678/head
Soby Mathew
9 years ago
4 changed files with 752 additions and 14 deletions
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* Redistributions of source code must retain the above copyright notice, this |
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* list of conditions and the following disclaimer. |
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* |
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* Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* |
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* Neither the name of ARM nor the names of its contributors may be used |
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* to endorse or promote products derived from this software without specific |
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* prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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#ifndef __ARCH_H__ |
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#define __ARCH_H__ |
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/*******************************************************************************
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* MIDR bit definitions |
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******************************************************************************/ |
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#define MIDR_IMPL_MASK 0xff |
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#define MIDR_IMPL_SHIFT 24 |
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#define MIDR_VAR_SHIFT 20 |
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#define MIDR_VAR_BITS 4 |
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#define MIDR_REV_SHIFT 0 |
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#define MIDR_REV_BITS 4 |
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#define MIDR_PN_MASK 0xfff |
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#define MIDR_PN_SHIFT 4 |
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/*******************************************************************************
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* MPIDR macros |
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******************************************************************************/ |
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#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK |
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#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) |
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#define MPIDR_AFFINITY_BITS 8 |
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#define MPIDR_AFFLVL_MASK 0xff |
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#define MPIDR_AFFLVL_SHIFT 3 |
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#define MPIDR_AFF0_SHIFT 0 |
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#define MPIDR_AFF1_SHIFT 8 |
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#define MPIDR_AFF2_SHIFT 16 |
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#define MPIDR_AFFINITY_MASK 0x00ffffff |
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#define MPIDR_AFFLVL0 0 |
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#define MPIDR_AFFLVL1 1 |
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#define MPIDR_AFFLVL2 2 |
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#define MPIDR_AFFLVL0_VAL(mpidr) \ |
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(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) |
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#define MPIDR_AFFLVL1_VAL(mpidr) \ |
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(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) |
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#define MPIDR_AFFLVL2_VAL(mpidr) \ |
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(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) |
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/*
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* The MPIDR_MAX_AFFLVL count starts from 0. Take care to |
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* add one while using this macro to define array sizes. |
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*/ |
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#define MPIDR_MAX_AFFLVL 2 |
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/* Data Cache set/way op type defines */ |
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#define DC_OP_ISW 0x0 |
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#define DC_OP_CISW 0x1 |
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#define DC_OP_CSW 0x2 |
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets |
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******************************************************************************/ |
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#define CNTCR_OFF 0x000 |
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#define CNTFID_OFF 0x020 |
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#define CNTCR_EN (1 << 0) |
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#define CNTCR_HDBG (1 << 1) |
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#define CNTCR_FCREQ(x) ((x) << 8) |
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/*******************************************************************************
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* System register bit definitions |
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******************************************************************************/ |
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/* CLIDR definitions */ |
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#define LOUIS_SHIFT 21 |
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#define LOC_SHIFT 24 |
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#define CLIDR_FIELD_WIDTH 3 |
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/* CSSELR definitions */ |
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#define LEVEL_SHIFT 1 |
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/* ID_PFR1 definitions */ |
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#define ID_PFR1_VIRTEXT_SHIFT 12 |
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#define ID_PFR1_VIRTEXT_MASK 0xf |
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#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ |
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& ID_PFR1_VIRTEXT_MASK) |
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#define ID_PFR1_GIC_SHIFT 28 |
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#define ID_PFR1_GIC_MASK 0xf |
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/* SCTLR definitions */ |
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#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ |
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(1 << 3) | SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT) |
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#define SCTLR_M_BIT (1 << 0) |
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#define SCTLR_A_BIT (1 << 1) |
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#define SCTLR_C_BIT (1 << 2) |
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#define SCTLR_CP15BEN_BIT (1 << 5) |
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#define SCTLR_ITD_BIT (1 << 7) |
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#define SCTLR_I_BIT (1 << 12) |
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#define SCTLR_V_BIT (1 << 13) |
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#define SCTLR_NTWI_BIT (1 << 16) |
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#define SCTLR_NTWE_BIT (1 << 18) |
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#define SCTLR_WXN_BIT (1 << 19) |
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#define SCTLR_UWXN_BIT (1 << 20) |
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#define SCTLR_EE_BIT (1 << 25) |
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#define SCTLR_TRE_BIT (1 << 28) |
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#define SCTLR_AFE_BIT (1 << 29) |
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#define SCTLR_TE_BIT (1 << 30) |
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/* HSCTLR definitions */ |
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#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ |
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| (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \ |
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| (1 << 3) | HSCTLR_CP15BEN_BIT) |
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#define HSCTLR_M_BIT (1 << 0) |
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#define HSCTLR_A_BIT (1 << 1) |
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#define HSCTLR_C_BIT (1 << 2) |
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#define HSCTLR_CP15BEN_BIT (1 << 5) |
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#define HSCTLR_ITD_BIT (1 << 7) |
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#define HSCTLR_SED_BIT (1 << 8) |
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#define HSCTLR_I_BIT (1 << 12) |
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#define HSCTLR_WXN_BIT (1 << 19) |
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#define HSCTLR_EE_BIT (1 << 25) |
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#define HSCTLR_TE_BIT (1 << 30) |
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/* CPACR definitions */ |
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#define CPACR_FPEN(x) ((x) << 20) |
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#define CPACR_FP_TRAP_PL0 0x1 |
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#define CPACR_FP_TRAP_ALL 0x2 |
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#define CPACR_FP_TRAP_NONE 0x3 |
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/* SCR definitions */ |
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#define SCR_TWE_BIT (1 << 13) |
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#define SCR_TWI_BIT (1 << 12) |
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#define SCR_SIF_BIT (1 << 9) |
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#define SCR_HCE_BIT (1 << 8) |
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#define SCR_SCD_BIT (1 << 7) |
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#define SCR_NET_BIT (1 << 6) |
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#define SCR_AW_BIT (1 << 5) |
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#define SCR_FW_BIT (1 << 4) |
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#define SCR_EA_BIT (1 << 3) |
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#define SCR_FIQ_BIT (1 << 2) |
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#define SCR_IRQ_BIT (1 << 1) |
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#define SCR_NS_BIT (1 << 0) |
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#define SCR_VALID_BIT_MASK 0x33ff |
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#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT) |
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/* HCR definitions */ |
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#define HCR_AMO_BIT (1 << 5) |
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#define HCR_IMO_BIT (1 << 4) |
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#define HCR_FMO_BIT (1 << 3) |
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/* CNTHCTL definitions */ |
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#define EVNTEN_BIT (1 << 2) |
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#define PL1PCEN_BIT (1 << 1) |
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#define PL1PCTEN_BIT (1 << 0) |
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/* CNTKCTL definitions */ |
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#define PL0PTEN_BIT (1 << 9) |
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#define PL0VTEN_BIT (1 << 8) |
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#define PL0PCTEN_BIT (1 << 0) |
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#define PL0VCTEN_BIT (1 << 1) |
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#define EVNTEN_BIT (1 << 2) |
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#define EVNTDIR_BIT (1 << 3) |
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#define EVNTI_SHIFT 4 |
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#define EVNTI_MASK 0xf |
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/* HCPTR definitions */ |
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#define TCPAC_BIT (1 << 31) |
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#define TTA_BIT (1 << 20) |
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#define TCP11_BIT (1 << 10) |
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#define TCP10_BIT (1 << 10) |
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/* NASCR definitions */ |
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#define NSASEDIS_BIT (1 << 15) |
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#define NASCR_CP11_BIT (1 << 11) |
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#define NASCR_CP10_BIT (1 << 10) |
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/* CPACR definitions */ |
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#define ASEDIS_BIT (1 << 31) |
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#define TRCDIS_BIT (1 << 28) |
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#define CPACR_CP11_SHIFT 22 |
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#define CPACR_CP10_SHIFT 20 |
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#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\ |
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0x3 << CPACR_CP10_SHIFT) |
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/* FPEXC definitions */ |
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#define FPEXC_EN_BIT (1 << 30) |
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/* SPSR/CPSR definitions */ |
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#define SPSR_FIQ_BIT (1 << 0) |
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#define SPSR_IRQ_BIT (1 << 1) |
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#define SPSR_ABT_BIT (1 << 2) |
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#define SPSR_AIF_SHIFT 6 |
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#define SPSR_AIF_MASK 0x7 |
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#define SPSR_E_SHIFT 9 |
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#define SPSR_E_MASK 0x1 |
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#define SPSR_E_LITTLE 0 |
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#define SPSR_E_BIG 1 |
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#define SPSR_T_SHIFT 5 |
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#define SPSR_T_MASK 0x1 |
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#define SPSR_T_ARM 0 |
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#define SPSR_T_THUMB 1 |
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#define SPSR_MODE_SHIFT 0 |
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#define SPSR_MODE_MASK 0x7 |
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#define DISABLE_ALL_EXCEPTIONS \ |
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(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT) |
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/*
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* TTBCR definitions |
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*/ |
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/* The ARM Trusted Firmware uses the long descriptor format */ |
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#define TTBCR_EAE_BIT (1 << 31) |
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#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28) |
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#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28) |
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#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28) |
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#define TTBCR_RGN1_OUTER_NC (0x0 << 26) |
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#define TTBCR_RGN1_OUTER_WBA (0x1 << 26) |
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#define TTBCR_RGN1_OUTER_WT (0x2 << 26) |
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#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26) |
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#define TTBCR_RGN1_INNER_NC (0x0 << 24) |
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#define TTBCR_RGN1_INNER_WBA (0x1 << 24) |
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#define TTBCR_RGN1_INNER_WT (0x2 << 24) |
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#define TTBCR_RGN1_INNER_WBNA (0x3 << 24) |
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#define TTBCR_EPD1_BIT (1 << 23) |
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#define TTBCR_A1_BIT (1 << 22) |
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#define TTBCR_T1SZ_SHIFT 16 |
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#define TTBCR_T1SZ_MASK (0x7) |
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#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12) |
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#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12) |
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#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12) |
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#define TTBCR_RGN0_OUTER_NC (0x0 << 10) |
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#define TTBCR_RGN0_OUTER_WBA (0x1 << 10) |
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#define TTBCR_RGN0_OUTER_WT (0x2 << 10) |
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#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10) |
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#define TTBCR_RGN0_INNER_NC (0x0 << 8) |
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#define TTBCR_RGN0_INNER_WBA (0x1 << 8) |
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#define TTBCR_RGN0_INNER_WT (0x2 << 8) |
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#define TTBCR_RGN0_INNER_WBNA (0x3 << 8) |
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#define TTBCR_EPD0_BIT (1 << 7) |
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#define TTBCR_T0SZ_SHIFT 0 |
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#define TTBCR_T0SZ_MASK (0x7) |
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#define MODE_RW_SHIFT 0x4 |
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#define MODE_RW_MASK 0x1 |
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#define MODE_RW_32 0x1 |
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#define MODE32_SHIFT 0 |
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#define MODE32_MASK 0x1f |
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#define MODE32_usr 0x10 |
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#define MODE32_fiq 0x11 |
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#define MODE32_irq 0x12 |
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#define MODE32_svc 0x13 |
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#define MODE32_mon 0x16 |
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#define MODE32_abt 0x17 |
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#define MODE32_hyp 0x1a |
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#define MODE32_und 0x1b |
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#define MODE32_sys 0x1f |
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#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) |
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#define SPSR_MODE32(mode, isa, endian, aif) \ |
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(MODE_RW_32 << MODE_RW_SHIFT | \ |
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((mode) & MODE32_MASK) << MODE32_SHIFT | \ |
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((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ |
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((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ |
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) |
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/*
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* CTR definitions |
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*/ |
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#define CTR_CWG_SHIFT 24 |
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#define CTR_CWG_MASK 0xf |
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#define CTR_ERG_SHIFT 20 |
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#define CTR_ERG_MASK 0xf |
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#define CTR_DMINLINE_SHIFT 16 |
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#define CTR_DMINLINE_WIDTH 4 |
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#define CTR_DMINLINE_MASK ((1 << 4) - 1) |
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#define CTR_L1IP_SHIFT 14 |
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#define CTR_L1IP_MASK 0x3 |
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#define CTR_IMINLINE_SHIFT 0 |
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#define CTR_IMINLINE_MASK 0xf |
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#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */ |
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/*******************************************************************************
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the |
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* system level implementation of the Generic Timer. |
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******************************************************************************/ |
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#define CNTNSAR 0x4 |
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#define CNTNSAR_NS_SHIFT(x) (x) |
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#define CNTACR_BASE(x) (0x40 + ((x) << 2)) |
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#define CNTACR_RPCT_SHIFT 0x0 |
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#define CNTACR_RVCT_SHIFT 0x1 |
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#define CNTACR_RFRQ_SHIFT 0x2 |
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#define CNTACR_RVOFF_SHIFT 0x3 |
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#define CNTACR_RWVT_SHIFT 0x4 |
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#define CNTACR_RWPT_SHIFT 0x5 |
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/* MAIR macros */ |
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3)) |
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3)) |
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/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ |
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#define SCR p15, 0, c1, c1, 0 |
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#define SCTLR p15, 0, c1, c0, 0 |
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#define MPIDR p15, 0, c0, c0, 5 |
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#define MIDR p15, 0, c0, c0, 0 |
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#define VBAR p15, 0, c12, c0, 0 |
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#define MVBAR p15, 0, c12, c0, 1 |
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#define NSACR p15, 0, c1, c1, 2 |
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#define CPACR p15, 0, c1, c0, 2 |
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#define DCCIMVAC p15, 0, c7, c14, 1 |
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#define DCCMVAC p15, 0, c7, c10, 1 |
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#define DCIMVAC p15, 0, c7, c6, 1 |
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#define DCCISW p15, 0, c7, c14, 2 |
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#define DCCSW p15, 0, c7, c10, 2 |
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#define DCISW p15, 0, c7, c6, 2 |
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#define CTR p15, 0, c0, c0, 1 |
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#define CNTFRQ p15, 0, c14, c0, 0 |
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#define ID_PFR1 p15, 0, c0, c1, 1 |
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#define MAIR0 p15, 0, c10, c2, 0 |
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#define MAIR1 p15, 0, c10, c2, 1 |
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#define TTBCR p15, 0, c2, c0, 2 |
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#define TTBR0 p15, 0, c2, c0, 0 |
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#define TTBR1 p15, 0, c2, c0, 1 |
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#define TLBIALL p15, 0, c8, c7, 0 |
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#define TLBIALLIS p15, 0, c8, c3, 0 |
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#define TLBIMVA p15, 0, c8, c7, 1 |
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#define TLBIMVAA p15, 0, c8, c7, 3 |
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#define HSCTLR p15, 4, c1, c0, 0 |
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#define HCR p15, 4, c1, c1, 0 |
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#define HCPTR p15, 4, c1, c1, 2 |
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#define CNTHCTL p15, 4, c14, c1, 0 |
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#define VPIDR p15, 4, c0, c0, 0 |
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#define VMPIDR p15, 4, c0, c0, 5 |
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#define ISR p15, 0, c12, c1, 0 |
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#define CLIDR p15, 1, c0, c0, 1 |
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#define CSSELR p15, 2, c0, c0, 0 |
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#define CCSIDR p15, 1, c0, c0, 0 |
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/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */ |
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#define ICC_IAR1 p15, 0, c12, c12, 0 |
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#define ICC_IAR0 p15, 0, c12, c8, 0 |
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#define ICC_EOIR1 p15, 0, c12, c12, 1 |
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#define ICC_EOIR0 p15, 0, c12, c8, 1 |
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#define ICC_HPPIR1 p15, 0, c12, c12, 2 |
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#define ICC_HPPIR0 p15, 0, c12, c8, 2 |
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#define ICC_BPR1 p15, 0, c12, c12, 3 |
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#define ICC_BPR0 p15, 0, c12, c8, 3 |
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#define ICC_DIR p15, 0, c12, c11, 1 |
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#define ICC_PMR p15, 0, c4, c6, 0 |
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#define ICC_RPR p15, 0, c12, c11, 3 |
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#define ICC_CTLR p15, 0, c12, c12, 4 |
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#define ICC_MCTLR p15, 6, c12, c12, 4 |
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#define ICC_SRE p15, 0, c12, c12, 5 |
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#define ICC_HSRE p15, 4, c12, c9, 5 |
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#define ICC_MSRE p15, 6, c12, c12, 5 |
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#define ICC_IGRPEN0 p15, 0, c12, c12, 6 |
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#define ICC_IGRPEN1 p15, 0, c12, c12, 7 |
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#define ICC_MGRPEN1 p15, 6, c12, c12, 7 |
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/* 64 bit system register defines The format is: coproc, opt1, CRm */ |
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#define TTBR0_64 p15, 0, c2 |
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#define TTBR1_64 p15, 1, c2 |
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#define CNTVOFF_64 p15, 4, c14 |
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#define VTTBR_64 p15, 6, c2 |
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#define CNTPCT_64 p15, 0, c14 |
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/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */ |
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#define ICC_SGI1R_EL1_64 p15, 0, c12 |
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#define ICC_ASGI1R_EL1_64 p15, 1, c12 |
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#define ICC_SGI0R_EL1_64 p15, 2, c12 |
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#endif /* __ARCH_H__ */ |
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@ -0,0 +1,292 @@ |
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
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* |
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* Redistribution and use in source and binary forms, with or without |
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* modification, are permitted provided that the following conditions are met: |
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* |
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* Redistributions of source code must retain the above copyright notice, this |
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* list of conditions and the following disclaimer. |
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* |
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* Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* |
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* Neither the name of ARM nor the names of its contributors may be used |
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* to endorse or promote products derived from this software without specific |
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* prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
|||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
|||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
|||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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* POSSIBILITY OF SUCH DAMAGE. |
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*/ |
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|
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#ifndef __ARCH_HELPERS_H__ |
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#define __ARCH_HELPERS_H__ |
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|
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#include <arch.h> /* for additional register definitions */ |
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#include <stdint.h> |
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#include <types.h> |
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|
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/**********************************************************************
|
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* Macros which create inline functions to read or write CPU system |
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* registers |
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*********************************************************************/ |
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|
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#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ |
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static inline void write_## _name(u_register_t v) \ |
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{ \ |
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ |
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} |
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|
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#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \ |
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static inline u_register_t read_ ## _name(void) \ |
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{ \ |
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u_register_t v; \ |
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__asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\ |
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return v; \ |
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} |
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|
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/*
|
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* The undocumented %Q and %R extended asm are used to implemented the below |
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* 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian |
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* systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and |
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* Big Endian systems generate the right instruction encoding. |
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*/ |
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#if !(__GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6)) |
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#error "GCC 4.6 or above is required to build AArch32 Trusted Firmware" |
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#endif |
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|
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#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \ |
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static inline void write64_## _name(uint64_t v) \ |
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{ \ |
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__asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\ |
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} |
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|
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#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \ |
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static inline uint64_t read64_## _name(void) \ |
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{ uint64_t v; \ |
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__asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\ |
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return v; \ |
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} |
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|
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#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ |
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static inline u_register_t read_ ## _name(void) \ |
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{ \ |
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u_register_t v; \ |
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__asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ |
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return v; \ |
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} |
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|
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#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ |
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static inline void write_ ## _name(u_register_t v) \ |
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{ \ |
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__asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ |
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} |
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|
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#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \ |
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static inline void write_ ## _name(const u_register_t v) \ |
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{ \ |
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__asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \ |
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} |
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|
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/* Define read function for coproc register */ |
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#define DEFINE_COPROCR_READ_FUNC(_name, ...) \ |
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) |
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|
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/* Define read & write function for coproc register */ |
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#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \ |
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \ |
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_DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__) |
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|
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/* Define 64 bit read function for coproc register */ |
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#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \ |
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) |
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|
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/* Define 64 bit read & write function for coproc register */ |
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#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \ |
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \ |
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_DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__) |
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|
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/* Define read & write function for system register */ |
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#define DEFINE_SYSREG_RW_FUNCS(_name) \ |
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_DEFINE_SYSREG_READ_FUNC(_name, _name) \ |
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_DEFINE_SYSREG_WRITE_FUNC(_name, _name) |
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|
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/**********************************************************************
|
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* Macros to create inline functions for tlbi operations |
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*********************************************************************/ |
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|
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#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ |
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static inline void tlbi##_op(void) \ |
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{ \ |
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u_register_t v = 0; \ |
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ |
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} |
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|
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#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ |
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static inline void tlbi##_op(u_register_t v) \ |
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{ \ |
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ |
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} |
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|
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/* Define function for simple TLBI operation */ |
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#define DEFINE_TLBIOP_FUNC(_op, ...) \ |
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_DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__) |
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|
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/* Define function for TLBI operation with register parameter */ |
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#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \ |
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_DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__) |
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|
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/**********************************************************************
|
|||
* Macros to create inline functions for DC operations |
|||
*********************************************************************/ |
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#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \ |
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static inline void dc##_op(u_register_t v) \ |
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{ \ |
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\ |
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} |
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|
|||
/* Define function for DC operation with register parameter */ |
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#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \ |
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_DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__) |
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|
|||
/**********************************************************************
|
|||
* Macros to create inline functions for system instructions |
|||
*********************************************************************/ |
|||
/* Define function for simple system instruction */ |
|||
#define DEFINE_SYSOP_FUNC(_op) \ |
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static inline void _op(void) \ |
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{ \ |
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__asm__ (#_op); \ |
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} |
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|
|||
|
|||
/* Define function for system instruction with type specifier */ |
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#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ |
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static inline void _op ## _type(void) \ |
|||
{ \ |
|||
__asm__ (#_op " " #_type); \ |
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} |
|||
|
|||
/* Define function for system instruction with register parameter */ |
|||
#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ |
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static inline void _op ## _type(u_register_t v) \ |
|||
{ \ |
|||
__asm__ (#_op " " #_type ", %0" : : "r" (v)); \ |
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} |
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|
|||
void flush_dcache_range(uintptr_t addr, size_t size); |
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void clean_dcache_range(uintptr_t addr, size_t size); |
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void inv_dcache_range(uintptr_t addr, size_t size); |
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|
|||
DEFINE_SYSOP_FUNC(wfi) |
|||
DEFINE_SYSOP_FUNC(wfe) |
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DEFINE_SYSOP_FUNC(sev) |
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DEFINE_SYSOP_TYPE_FUNC(dsb, sy) |
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DEFINE_SYSOP_TYPE_FUNC(dmb, sy) |
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DEFINE_SYSOP_TYPE_FUNC(dsb, ish) |
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish) |
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DEFINE_SYSOP_FUNC(isb) |
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|
|||
DEFINE_SYSREG_RW_FUNCS(spsr) |
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DEFINE_SYSREG_RW_FUNCS(cpsr) |
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|
|||
/*******************************************************************************
|
|||
* System register accessor prototypes |
|||
******************************************************************************/ |
|||
DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR) |
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DEFINE_COPROCR_READ_FUNC(midr, MIDR) |
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DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1) |
|||
DEFINE_COPROCR_READ_FUNC(isr, ISR) |
|||
DEFINE_COPROCR_READ_FUNC(clidr, CLIDR) |
|||
DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64) |
|||
|
|||
DEFINE_COPROCR_RW_FUNCS(scr, SCR) |
|||
DEFINE_COPROCR_RW_FUNCS(ctr, CTR) |
|||
DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR) |
|||
DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR) |
|||
DEFINE_COPROCR_RW_FUNCS(hcr, HCR) |
|||
DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR) |
|||
DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ) |
|||
DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL) |
|||
DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0) |
|||
DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1) |
|||
DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR) |
|||
DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0) |
|||
DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64) |
|||
DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1) |
|||
DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR) |
|||
DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR) |
|||
DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64) |
|||
DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64) |
|||
DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64) |
|||
DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR) |
|||
|
|||
DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0) |
|||
DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1) |
|||
|
|||
/*
|
|||
* TLBI operation prototypes |
|||
*/ |
|||
DEFINE_TLBIOP_FUNC(all, TLBIALL) |
|||
DEFINE_TLBIOP_FUNC(allis, TLBIALLIS) |
|||
DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA) |
|||
DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA) |
|||
|
|||
/*
|
|||
* DC operation prototypes |
|||
*/ |
|||
DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC) |
|||
DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC) |
|||
DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC) |
|||
|
|||
/* Previously defined accessor functions with incomplete register names */ |
|||
#define dsb() dsbsy() |
|||
|
|||
#define IS_IN_SECURE() \ |
|||
(GET_NS_BIT(read_scr()) == 0) |
|||
|
|||
/*
|
|||
* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3 |
|||
*/ |
|||
#define IS_IN_EL3() \ |
|||
((GET_M32(read_cpsr()) == MODE32_mon) || \ |
|||
(IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr))) |
|||
|
|||
/* Macros for compatibility with AArch64 system registers */ |
|||
#define read_mpidr_el1() read_mpidr() |
|||
|
|||
#define read_scr_el3() read_scr() |
|||
#define write_scr_el3(_v) write_scr(_v) |
|||
|
|||
#define read_hcr_el2() read_hcr() |
|||
#define write_hcr_el2(_v) write_hcr(_v) |
|||
|
|||
#define read_cpacr_el1() read_cpacr() |
|||
#define write_cpacr_el1(_v) write_cpacr(_v) |
|||
|
|||
#define read_cntfrq_el0() read_cntfrq() |
|||
#define write_cntfrq_el0(_v) write_cntfrq(_v) |
|||
#define read_isr_el1() read_isr() |
|||
|
|||
#define read_cntpct_el0() read64_cntpct() |
|||
|
|||
#endif /* __ARCH_HELPERS_H__ */ |
|||
Loading…
Reference in new issue