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The EL3 runtime firmware has been running from internal trusted SRAM space on the Morello platform. Due to unavailability of tag support for the internal trusted SRAM this becomes a problem if we enable capability pointers in BL31. To support capability pointers in BL31 it has to be run from the main DDR memory space. This patch updates the Morello platform configuration such that BL31 is loaded and run from DDR space. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Change-Id: I16d4d757fb6f58c364f5133236d50fc06845e0b4pull/1986/head
Manoj Kumar
2 years ago
4 changed files with 227 additions and 223 deletions
@ -1,27 +1,226 @@ |
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved. |
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <common/debug.h> |
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#include <drivers/arm/css/sds.h> |
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#include <lib/mmio.h> |
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#include <lib/utils.h> |
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#include <plat/arm/common/plat_arm.h> |
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void bl2_platform_setup(void) |
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{ |
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#include "morello_def.h" |
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#include <platform_def.h> |
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#ifdef TARGET_PLATFORM_FVP |
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/*
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* Platform information structure stored in SDS. |
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* This structure holds information about platform's DDR |
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* size |
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* - Local DDR size in bytes, DDR memory in main board |
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*/ |
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struct morello_plat_info { |
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uint64_t local_ddr_size; |
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} __packed; |
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#else |
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/*
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* Platform information structure stored in SDS. |
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* This structure holds information about platform's DDR |
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* size which is an information about multichip setup |
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* - Local DDR size in bytes, DDR memory in main board |
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* - Remote DDR size in bytes, DDR memory in remote board |
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* - remote_chip_count |
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* - multichip mode |
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* - scc configuration |
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*/ |
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struct morello_plat_info { |
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uint64_t local_ddr_size; |
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uint64_t remote_ddr_size; |
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uint8_t remote_chip_count; |
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bool multichip_mode; |
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uint32_t scc_config; |
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} __packed; |
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#endif |
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/* Compile time assertion to ensure the size of structure is 18 bytes */ |
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CASSERT(sizeof(struct morello_plat_info) == MORELLO_SDS_PLATFORM_INFO_SIZE, |
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assert_invalid_plat_info_size); |
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#ifdef TARGET_PLATFORM_SOC |
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/*
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* Morello platform supports RDIMMs with ECC capability. To use the ECC |
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* capability, the entire DDR memory space has to be zeroed out before |
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* enabling the ECC bits in DMC-Bing. |
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* Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF during BL2 stage, |
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* as BL33 binary cannot be copied to DDR memory before enabling ECC. |
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* Rest of the DDR memory space is zeroed out during BL31 stage. |
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*/ |
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/*
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* Morello platform supports RDIMMs with ECC capability. To use the ECC |
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* capability, the entire DDR memory space has to be zeroed out before |
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* enabling the ECC bits in DMC-Bing. Zeroing out several gigabytes of |
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* memory from SCP is quite time consuming so the following function |
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* is added to zero out the DDR memory from application processor which is |
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* much faster compared to SCP. |
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*/ |
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static void dmc_ecc_setup(struct morello_plat_info *plat_info) |
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{ |
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uint64_t dram2_size; |
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uint32_t val; |
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uint64_t tag_mem_base; |
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uint64_t usable_mem_size; |
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INFO("Total DIMM size: %uGB\n", |
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(uint32_t)(plat_info->local_ddr_size / 0x40000000)); |
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assert(plat_info->local_ddr_size > ARM_DRAM1_SIZE); |
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dram2_size = plat_info->local_ddr_size - ARM_DRAM1_SIZE; |
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INFO("Zeroing DDR memory range 0x80000000 - 0xFFFFFFFF\n"); |
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zero_normalmem((void *)ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
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flush_dcache_range(ARM_DRAM1_BASE, ARM_DRAM1_SIZE); |
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INFO("Zeroing DDR memory range 0x%llx - 0x%llx\n", |
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ARM_DRAM2_BASE, ARM_DRAM2_BASE + dram2_size); |
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zero_normalmem((void *)ARM_DRAM2_BASE, dram2_size); |
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flush_dcache_range(ARM_DRAM2_BASE, dram2_size); |
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/* Clear previous ECC errors while zeroing out the memory */ |
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val = mmio_read_32(MORELLO_DMC0_ERR2STATUS_REG); |
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mmio_write_32(MORELLO_DMC0_ERR2STATUS_REG, val); |
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val = mmio_read_32(MORELLO_DMC1_ERR2STATUS_REG); |
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mmio_write_32(MORELLO_DMC1_ERR2STATUS_REG, val); |
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/* Set DMCs to CONFIG state before writing ERR0CTLR0 register */ |
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mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); |
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mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_CONFIG); |
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while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & |
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MORELLO_DMC_MEMC_STATUS_MASK) != |
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MORELLO_DMC_MEMC_CMD_CONFIG) { |
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continue; |
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} |
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while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & |
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MORELLO_DMC_MEMC_STATUS_MASK) != |
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MORELLO_DMC_MEMC_CMD_CONFIG) { |
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continue; |
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} |
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/* Configure Bing client/server mode based on SCC configuration */ |
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if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) { |
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INFO("Configuring DMC Bing in client mode\n"); |
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usable_mem_size = plat_info->local_ddr_size - |
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(plat_info->local_ddr_size / 128ULL); |
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/* Linear DDR address */ |
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tag_mem_base = usable_mem_size; |
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tag_mem_base = tag_mem_base / 4; |
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/* Reverse translation */ |
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if (tag_mem_base < ARM_DRAM1_BASE) { |
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tag_mem_base += ARM_DRAM1_BASE; |
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} else { |
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tag_mem_base = tag_mem_base - ARM_DRAM1_BASE + |
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ARM_DRAM2_BASE; |
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} |
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mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1); |
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mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1); |
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mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1); |
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mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1); |
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if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) { |
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mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2); |
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mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2); |
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INFO("C1 Tag Cache Enabled\n"); |
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} |
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if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) { |
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mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4); |
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mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4); |
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INFO("C2 Tag Cache Enabled\n"); |
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} |
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mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL, |
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(uint32_t)tag_mem_base); |
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mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL, |
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(uint32_t)tag_mem_base); |
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mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2, |
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(uint32_t)(tag_mem_base >> 32)); |
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mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2, |
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(uint32_t)(tag_mem_base >> 32)); |
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mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL, |
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MORELLO_DMC_MEM_ACCESS_DIS); |
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mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL, |
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MORELLO_DMC_MEM_ACCESS_DIS); |
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INFO("Tag base set to 0x%lx\n", tag_mem_base); |
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plat_info->local_ddr_size = usable_mem_size; |
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} else { |
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INFO("Configuring DMC Bing in server mode\n"); |
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mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0); |
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mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0); |
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} |
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INFO("Enabling ECC on DMCs\n"); |
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/* Enable ECC in DMCs */ |
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mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG, |
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MORELLO_DMC_ERR0CTLR0_ECC_EN); |
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mmio_setbits_32(MORELLO_DMC1_ERR0CTLR0_REG, |
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MORELLO_DMC_ERR0CTLR0_ECC_EN); |
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/* Set DMCs to READY state */ |
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mmio_write_32(MORELLO_DMC0_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); |
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mmio_write_32(MORELLO_DMC1_MEMC_CMD_REG, MORELLO_DMC_MEMC_CMD_READY); |
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while ((mmio_read_32(MORELLO_DMC0_MEMC_STATUS_REG) & |
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MORELLO_DMC_MEMC_STATUS_MASK) != |
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MORELLO_DMC_MEMC_CMD_READY) { |
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continue; |
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} |
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while ((mmio_read_32(MORELLO_DMC1_MEMC_STATUS_REG) & |
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MORELLO_DMC_MEMC_STATUS_MASK) != |
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MORELLO_DMC_MEMC_CMD_READY) { |
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continue; |
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} |
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} |
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#endif |
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void bl2_platform_setup(void) |
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{ |
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int ret; |
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struct morello_plat_info plat_info; |
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ret = sds_init(); |
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if (ret != SDS_OK) { |
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ERROR("SDS initialization failed. ret:%d\n", ret); |
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panic(); |
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} |
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ret = sds_struct_read(MORELLO_SDS_PLATFORM_INFO_STRUCT_ID, |
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MORELLO_SDS_PLATFORM_INFO_OFFSET, |
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&plat_info, |
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MORELLO_SDS_PLATFORM_INFO_SIZE, |
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SDS_ACCESS_MODE_NON_CACHED); |
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if (ret != SDS_OK) { |
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ERROR("Error getting platform info from SDS. ret:%d\n", ret); |
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panic(); |
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} |
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/* Validate plat_info SDS */ |
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#ifdef TARGET_PLATFORM_FVP |
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if (plat_info.local_ddr_size == 0U) { |
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#else |
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if ((plat_info.local_ddr_size == 0U) |
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|| (plat_info.local_ddr_size > MORELLO_MAX_DDR_CAPACITY) |
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|| (plat_info.remote_ddr_size > MORELLO_MAX_DDR_CAPACITY) |
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|| (plat_info.remote_chip_count > MORELLO_MAX_REMOTE_CHIP_COUNT) |
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) { |
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#endif |
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ERROR("platform info SDS is corrupted\n"); |
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panic(); |
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} |
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#ifdef TARGET_PLATFORM_SOC |
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dmc_ecc_setup(&plat_info); |
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#endif |
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arm_bl2_platform_setup(); |
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} |
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