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@ -44,35 +44,34 @@ |
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#include <tegra_private.h> |
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extern uint64_t tegra_bl31_phys_base; |
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extern uint64_t sec_entry_point[PLATFORM_CORE_COUNT]; |
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static int system_suspended; |
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extern uint64_t tegra_sec_entry_point; |
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/*
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* The following platform setup functions are weakly defined. They |
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* provide typical implementations that will be overridden by a SoC. |
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*/ |
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#pragma weak tegra_soc_prepare_cpu_suspend |
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#pragma weak tegra_soc_prepare_cpu_on |
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#pragma weak tegra_soc_prepare_cpu_off |
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#pragma weak tegra_soc_prepare_cpu_on_finish |
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#pragma weak tegra_soc_pwr_domain_suspend |
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#pragma weak tegra_soc_pwr_domain_on |
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#pragma weak tegra_soc_pwr_domain_off |
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#pragma weak tegra_soc_pwr_domain_on_finish |
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#pragma weak tegra_soc_prepare_system_reset |
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int tegra_soc_prepare_cpu_suspend(unsigned int id, unsigned int afflvl) |
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
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{ |
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return PSCI_E_NOT_SUPPORTED; |
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} |
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int tegra_soc_prepare_cpu_on(unsigned long mpidr) |
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int tegra_soc_pwr_domain_on(u_register_t mpidr) |
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{ |
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return PSCI_E_SUCCESS; |
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} |
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int tegra_soc_prepare_cpu_off(unsigned long mpidr) |
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
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{ |
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return PSCI_E_SUCCESS; |
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} |
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int tegra_soc_prepare_cpu_on_finish(unsigned long mpidr) |
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int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
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{ |
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return PSCI_E_SUCCESS; |
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} |
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@ -83,33 +82,25 @@ int tegra_soc_prepare_system_reset(void) |
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} |
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/*******************************************************************************
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* Track system suspend entry. |
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******************************************************************************/ |
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void tegra_pm_system_suspend_entry(void) |
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{ |
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system_suspended = 1; |
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} |
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/*******************************************************************************
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* Track system suspend exit. |
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******************************************************************************/ |
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void tegra_pm_system_suspend_exit(void) |
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
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* call to get the `power_state` parameter. This allows the platform to encode |
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* the appropriate State-ID field within the `power_state` parameter which can |
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* be utilized in `pwr_domain_suspend()` to suspend to system affinity level. |
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******************************************************************************/ |
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void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) |
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{ |
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system_suspended = 0; |
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} |
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/* lower affinities use PLAT_MAX_OFF_STATE */ |
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for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
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/*******************************************************************************
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* Get the system suspend state. |
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******************************************************************************/ |
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int tegra_system_suspended(void) |
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{ |
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return system_suspended; |
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/* max affinity uses system suspend state id */ |
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN; |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance is about to enter standby. |
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******************************************************************************/ |
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void tegra_affinst_standby(unsigned int power_state) |
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void tegra_cpu_standby(plat_local_state_t cpu_state) |
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{ |
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/*
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* Enter standby state |
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@ -119,132 +110,45 @@ void tegra_affinst_standby(unsigned int power_state) |
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wfi(); |
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} |
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
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* call to get the `power_state` parameter. This allows the platform to encode |
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* the appropriate State-ID field within the `power_state` parameter which can |
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* be utilized in `affinst_suspend()` to suspend to system affinity level. |
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******************************************************************************/ |
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unsigned int tegra_get_sys_suspend_power_state(void) |
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{ |
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unsigned int power_state; |
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power_state = psci_make_powerstate(PLAT_SYS_SUSPEND_STATE_ID, |
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PSTATE_TYPE_POWERDOWN, MPIDR_AFFLVL2); |
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return power_state; |
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} |
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter. |
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******************************************************************************/ |
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int32_t tegra_validate_power_state(unsigned int power_state) |
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{ |
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return tegra_soc_validate_power_state(power_state); |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned on. The |
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* level and mpidr determine the affinity instance. |
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******************************************************************************/ |
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int tegra_affinst_on(unsigned long mpidr, |
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unsigned long sec_entrypoint, |
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unsigned int afflvl, |
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unsigned int state) |
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int tegra_pwr_domain_on(u_register_t mpidr) |
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{ |
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int cpu = mpidr & MPIDR_CPU_MASK; |
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/*
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* Support individual CPU power on only. |
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*/ |
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if (afflvl > MPIDR_AFFLVL0) |
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return PSCI_E_SUCCESS; |
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/*
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* Flush entrypoint variable to PoC since it will be |
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* accessed after a reset with the caches turned off. |
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*/ |
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sec_entry_point[cpu] = sec_entrypoint; |
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t)); |
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return tegra_soc_prepare_cpu_on(mpidr); |
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return tegra_soc_pwr_domain_on(mpidr); |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance is about to be turned off. The |
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* level determines the affinity instance. The 'state' arg. allows the |
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* platform to decide whether the cluster is being turned off and take apt |
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* actions. |
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* |
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* CAUTION: This function is called with coherent stacks so that caches can be |
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* turned off, flushed and coherency disabled. There is no guarantee that caches |
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* will remain turned on across calls to this function as each affinity level is |
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* dealt with. So do not write & read global variables across calls. It will be |
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* wise to do flush a write to the global to prevent unpredictable results. |
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* Handler called when a power domain is about to be turned off. The |
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* target_state encodes the power state that each level should transition to. |
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******************************************************************************/ |
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void tegra_affinst_off(unsigned int afflvl, unsigned int state) |
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void tegra_pwr_domain_off(const psci_power_state_t *target_state) |
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{ |
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/*
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* Support individual CPU power off only. |
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*/ |
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if (afflvl > MPIDR_AFFLVL0) |
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return; |
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tegra_soc_prepare_cpu_off(read_mpidr()); |
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tegra_soc_pwr_domain_off(target_state); |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance is about to be suspended. The |
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* level and mpidr determine the affinity instance. The 'state' arg. allows the |
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* platform to decide whether the cluster is being turned off and take apt |
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* actions. |
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* |
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* CAUTION: This function is called with coherent stacks so that caches can be |
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* turned off, flushed and coherency disabled. There is no guarantee that caches |
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* will remain turned on across calls to this function as each affinity level is |
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* dealt with. So do not write & read global variables across calls. It will be |
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* wise to flush a write to the global variable, to prevent unpredictable |
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* results. |
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* Handler called when called when a power domain is about to be suspended. The |
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* target_state encodes the power state that each level should transition to. |
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******************************************************************************/ |
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void tegra_affinst_suspend(unsigned long sec_entrypoint, |
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unsigned int afflvl, |
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unsigned int state) |
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void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) |
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{ |
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int id = psci_get_suspend_stateid(); |
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int cpu = read_mpidr() & MPIDR_CPU_MASK; |
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if (afflvl > PLATFORM_MAX_AFFLVL) |
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return; |
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/*
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* Flush entrypoint variable to PoC since it will be |
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* accessed after a reset with the caches turned off. |
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*/ |
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sec_entry_point[cpu] = sec_entrypoint; |
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flush_dcache_range((uint64_t)&sec_entry_point[cpu], sizeof(uint64_t)); |
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tegra_soc_prepare_cpu_suspend(id, afflvl); |
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tegra_soc_pwr_domain_suspend(target_state); |
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/* disable GICC */ |
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tegra_gic_cpuif_deactivate(); |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after |
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* being turned off earlier. The level determines the affinity instance. |
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* The 'state' arg. allows the platform to decide whether the cluster was |
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* turned off prior to wakeup and do what's necessary to set it up. |
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* Handler called when a power domain has just been powered on after |
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* being turned off earlier. The target_state encodes the low power state that |
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* each level has woken up from. |
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******************************************************************************/ |
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void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state) |
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void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) |
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{ |
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plat_params_from_bl2_t *plat_params; |
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/*
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* Support individual CPU power on only. |
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*/ |
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if (afflvl > MPIDR_AFFLVL0) |
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return; |
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/*
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* Initialize the GIC cpu and distributor interfaces |
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*/ |
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@ -253,7 +157,8 @@ void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state) |
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/*
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* Check if we are exiting from deep sleep. |
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*/ |
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if (tegra_system_suspended()) { |
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if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
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PSTATE_ID_SOC_POWERDN) { |
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/*
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* Lock scratch registers which hold the CPU vectors. |
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@ -276,18 +181,17 @@ void tegra_affinst_on_finish(unsigned int afflvl, unsigned int state) |
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/*
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* Reset hardware settings. |
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*/ |
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tegra_soc_prepare_cpu_on_finish(read_mpidr()); |
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tegra_soc_pwr_domain_on_finish(target_state); |
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} |
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/*******************************************************************************
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* Handler called when an affinity instance has just been powered on after |
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* having been suspended earlier. The level and mpidr determine the affinity |
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* instance. |
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* Handler called when a power domain has just been powered on after |
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* having been suspended earlier. The target_state encodes the low power state |
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* that each level has woken up from. |
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******************************************************************************/ |
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void tegra_affinst_suspend_finish(unsigned int afflvl, unsigned int state) |
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void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
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{ |
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if (afflvl == MPIDR_AFFLVL0) |
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tegra_affinst_on_finish(afflvl, state); |
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tegra_pwr_domain_on_finish(target_state); |
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} |
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/*******************************************************************************
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@ -313,36 +217,78 @@ __dead2 void tegra_system_reset(void) |
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tegra_pmc_system_reset(); |
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} |
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/*******************************************************************************
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* Handler called to check the validity of the power state parameter. |
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******************************************************************************/ |
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int32_t tegra_validate_power_state(unsigned int power_state, |
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psci_power_state_t *req_state) |
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{ |
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int pwr_lvl = psci_get_pstate_pwrlvl(power_state); |
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assert(req_state); |
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if (pwr_lvl > PLAT_MAX_PWR_LVL) |
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return PSCI_E_INVALID_PARAMS; |
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return tegra_soc_validate_power_state(power_state, req_state); |
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} |
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/*******************************************************************************
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* Platform handler called to check the validity of the non secure entrypoint. |
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******************************************************************************/ |
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int tegra_validate_ns_entrypoint(uintptr_t entrypoint) |
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{ |
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/*
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* Check if the non secure entrypoint lies within the non |
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* secure DRAM. |
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*/ |
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if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) |
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return PSCI_E_SUCCESS; |
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return PSCI_E_INVALID_ADDRESS; |
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} |
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them |
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******************************************************************************/ |
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static const plat_pm_ops_t tegra_plat_pm_ops = { |
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.affinst_standby = tegra_affinst_standby, |
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.affinst_on = tegra_affinst_on, |
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.affinst_off = tegra_affinst_off, |
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.affinst_suspend = tegra_affinst_suspend, |
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.affinst_on_finish = tegra_affinst_on_finish, |
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.affinst_suspend_finish = tegra_affinst_suspend_finish, |
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static const plat_psci_ops_t tegra_plat_psci_ops = { |
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.cpu_standby = tegra_cpu_standby, |
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.pwr_domain_on = tegra_pwr_domain_on, |
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.pwr_domain_off = tegra_pwr_domain_off, |
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.pwr_domain_suspend = tegra_pwr_domain_suspend, |
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.pwr_domain_on_finish = tegra_pwr_domain_on_finish, |
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.pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, |
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.system_off = tegra_system_off, |
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.system_reset = tegra_system_reset, |
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.validate_power_state = tegra_validate_power_state, |
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.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state |
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.validate_ns_entrypoint = tegra_validate_ns_entrypoint, |
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.get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, |
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}; |
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/*******************************************************************************
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* Export the platform specific power ops & initialize the fvp power controller |
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* Export the platform specific power ops and initialize Power Controller |
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******************************************************************************/ |
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int platform_setup_pm(const plat_pm_ops_t **plat_ops) |
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int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
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const plat_psci_ops_t **psci_ops) |
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{ |
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psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; |
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/*
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* Flush entrypoint variable to PoC since it will be |
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* accessed after a reset with the caches turned off. |
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*/ |
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tegra_sec_entry_point = sec_entrypoint; |
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flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); |
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/*
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* Reset hardware settings. |
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*/ |
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tegra_soc_prepare_cpu_on_finish(read_mpidr()); |
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tegra_soc_pwr_domain_on_finish(&target_state); |
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/*
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* Initialize PM ops struct |
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* Initialize PSCI ops struct |
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*/ |
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*plat_ops = &tegra_plat_pm_ops; |
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*psci_ops = &tegra_plat_psci_ops; |
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return 0; |
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} |
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danh-arm
9 years ago