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When the source code says 'SMCC' it is talking about the SMC Calling Convention. The correct acronym is SMCCC. This affects a few definitions and file names. Some files have been renamed (smcc.h, smcc_helpers.h and smcc_macros.S) but the old files have been kept for compatibility, they include the new ones with an ERROR_DEPRECATED guard. Change-Id: I78f94052a502436fdd97ca32c0fe86bd58173f2f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>pull/1314/head
Antonio Nino Diaz
7 years ago
28 changed files with 617 additions and 558 deletions
@ -1,199 +1,15 @@ |
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/* |
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. |
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __SMCC_MACROS_S__ |
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#define __SMCC_MACROS_S__ |
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|
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#include <arch.h> |
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#if !ERROR_DEPRECATED |
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#include <smccc_macros.S> |
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|
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/* |
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* Macro to save the General purpose registers (r0 - r12), the banked |
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* spsr, lr, sp registers and the `scr` register to the SMC context on entry |
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* due a SMC call. The `lr` of the current mode (monitor) is expected to be |
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* already saved. The `sp` must point to the `smc_ctx_t` to save to. |
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* Additionally, also save the 'pmcr' register as this is updated whilst |
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* executing in the secure world. |
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*/ |
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.macro smcc_save_gp_mode_regs |
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/* Save r0 - r12 in the SMC context */ |
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stm sp, {r0-r12} |
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mov r0, sp |
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add r0, r0, #SMC_CTX_SP_USR |
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|
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#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) |
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/* Must be in secure state to restore Monitor mode */ |
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ldcopr r4, SCR |
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bic r2, r4, #SCR_NS_BIT |
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stcopr r2, SCR |
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isb |
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|
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cps #MODE32_sys |
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stm r0!, {sp, lr} |
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|
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cps #MODE32_irq |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_fiq |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_svc |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_abt |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_und |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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/* lr_mon is already saved by caller */ |
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cps #MODE32_mon |
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mrs r2, spsr |
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stm r0!, {r2} |
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|
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stcopr r4, SCR |
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isb |
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#else |
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/* Save the banked registers including the current SPSR and LR */ |
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mrs r4, sp_usr |
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mrs r5, lr_usr |
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mrs r6, spsr_irq |
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mrs r7, sp_irq |
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mrs r8, lr_irq |
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mrs r9, spsr_fiq |
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mrs r10, sp_fiq |
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mrs r11, lr_fiq |
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mrs r12, spsr_svc |
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stm r0!, {r4-r12} |
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|
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mrs r4, sp_svc |
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mrs r5, lr_svc |
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mrs r6, spsr_abt |
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mrs r7, sp_abt |
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mrs r8, lr_abt |
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mrs r9, spsr_und |
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mrs r10, sp_und |
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mrs r11, lr_und |
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mrs r12, spsr |
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stm r0!, {r4-r12} |
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/* lr_mon is already saved by caller */ |
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|
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ldcopr r4, SCR |
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#endif |
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str r4, [sp, #SMC_CTX_SCR] |
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ldcopr r4, PMCR |
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str r4, [sp, #SMC_CTX_PMCR] |
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.endm |
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|
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/* |
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* Macro to restore the `smc_ctx_t`, which includes the General purpose |
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* registers and banked mode registers, and exit from the monitor mode. |
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* r0 must point to the `smc_ctx_t` to restore from. |
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*/ |
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.macro monitor_exit |
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/* |
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* Save the current sp and restore the smc context |
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* pointer to sp which will be used for handling the |
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* next SMC. |
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*/ |
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str sp, [r0, #SMC_CTX_SP_MON] |
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mov sp, r0 |
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|
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/* |
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* Restore SCR first so that we access the right banked register |
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* when the other mode registers are restored. |
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*/ |
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ldr r1, [r0, #SMC_CTX_SCR] |
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stcopr r1, SCR |
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isb |
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|
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/* |
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* Restore the PMCR register. |
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*/ |
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ldr r1, [r0, #SMC_CTX_PMCR] |
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stcopr r1, PMCR |
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|
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/* Restore the banked registers including the current SPSR */ |
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add r1, r0, #SMC_CTX_SP_USR |
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|
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#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) |
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/* Must be in secure state to restore Monitor mode */ |
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ldcopr r4, SCR |
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bic r2, r4, #SCR_NS_BIT |
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stcopr r2, SCR |
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isb |
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|
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cps #MODE32_sys |
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ldm r1!, {sp, lr} |
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|
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cps #MODE32_irq |
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ldm r1!, {r2, sp, lr} |
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msr spsr_fsxc, r2 |
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|
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cps #MODE32_fiq |
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ldm r1!, {r2, sp, lr} |
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msr spsr_fsxc, r2 |
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|
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cps #MODE32_svc |
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ldm r1!, {r2, sp, lr} |
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msr spsr_fsxc, r2 |
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|
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cps #MODE32_abt |
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ldm r1!, {r2, sp, lr} |
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msr spsr_fsxc, r2 |
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|
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cps #MODE32_und |
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ldm r1!, {r2, sp, lr} |
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msr spsr_fsxc, r2 |
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|
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cps #MODE32_mon |
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ldm r1!, {r2} |
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msr spsr_fsxc, r2 |
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|
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stcopr r4, SCR |
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isb |
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#else |
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ldm r1!, {r4-r12} |
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msr sp_usr, r4 |
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msr lr_usr, r5 |
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msr spsr_irq, r6 |
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msr sp_irq, r7 |
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msr lr_irq, r8 |
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msr spsr_fiq, r9 |
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msr sp_fiq, r10 |
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msr lr_fiq, r11 |
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msr spsr_svc, r12 |
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|
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ldm r1!, {r4-r12} |
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msr sp_svc, r4 |
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msr lr_svc, r5 |
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msr spsr_abt, r6 |
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msr sp_abt, r7 |
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msr lr_abt, r8 |
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msr spsr_und, r9 |
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msr sp_und, r10 |
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msr lr_und, r11 |
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/* |
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* Use the `_fsxc` suffix explicitly to instruct the assembler |
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* to update all the 32 bits of SPSR. Else, by default, the |
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* assembler assumes `_fc` suffix which only modifies |
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* f->[31:24] and c->[7:0] bits of SPSR. |
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*/ |
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msr spsr_fsxc, r12 |
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#define smcc_save_gp_mode_regs smccc_save_gp_mode_regs |
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#endif |
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|
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/* Restore the LR */ |
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ldr lr, [r0, #SMC_CTX_LR_MON] |
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|
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/* Restore the rest of the general purpose registers */ |
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ldm r0, {r0-r12} |
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eret |
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.endm |
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|
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#endif /* __SMCC_MACROS_S__ */ |
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|
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@ -0,0 +1,166 @@ |
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/*
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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|
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#ifndef __SMCCC_HELPERS_H__ |
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#define __SMCCC_HELPERS_H__ |
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|
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#include <smccc.h> |
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|
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/* These are offsets to registers in smc_ctx_t */ |
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#define SMC_CTX_GPREG_R0 0x0 |
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#define SMC_CTX_GPREG_R1 0x4 |
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#define SMC_CTX_GPREG_R2 0x8 |
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#define SMC_CTX_GPREG_R3 0xC |
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#define SMC_CTX_GPREG_R4 0x10 |
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#define SMC_CTX_GPREG_R5 0x14 |
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#define SMC_CTX_SP_USR 0x34 |
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#define SMC_CTX_SPSR_MON 0x78 |
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#define SMC_CTX_SP_MON 0x7C |
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#define SMC_CTX_LR_MON 0x80 |
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#define SMC_CTX_SCR 0x84 |
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#define SMC_CTX_PMCR 0x88 |
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#define SMC_CTX_SIZE 0x90 |
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|
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#ifndef __ASSEMBLY__ |
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#include <cassert.h> |
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#include <types.h> |
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|
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/*
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* The generic structure to save arguments and callee saved registers during |
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* an SMC. Also this structure is used to store the result return values after |
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* the completion of SMC service. |
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*/ |
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typedef struct smc_ctx { |
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u_register_t r0; |
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u_register_t r1; |
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u_register_t r2; |
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u_register_t r3; |
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u_register_t r4; |
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u_register_t r5; |
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u_register_t r6; |
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u_register_t r7; |
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u_register_t r8; |
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u_register_t r9; |
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u_register_t r10; |
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u_register_t r11; |
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u_register_t r12; |
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/* spsr_usr doesn't exist */ |
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u_register_t sp_usr; |
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u_register_t lr_usr; |
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u_register_t spsr_irq; |
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u_register_t sp_irq; |
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u_register_t lr_irq; |
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u_register_t spsr_fiq; |
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u_register_t sp_fiq; |
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u_register_t lr_fiq; |
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u_register_t spsr_svc; |
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u_register_t sp_svc; |
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u_register_t lr_svc; |
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u_register_t spsr_abt; |
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u_register_t sp_abt; |
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u_register_t lr_abt; |
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u_register_t spsr_und; |
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u_register_t sp_und; |
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u_register_t lr_und; |
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u_register_t spsr_mon; |
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/*
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* `sp_mon` will point to the C runtime stack in monitor mode. But prior |
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* to exit from SMC, this will point to the `smc_ctx_t` so that |
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* on next entry due to SMC, the `smc_ctx_t` can be easily accessed. |
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*/ |
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u_register_t sp_mon; |
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u_register_t lr_mon; |
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u_register_t scr; |
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u_register_t pmcr; |
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/*
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* The workaround for CVE-2017-5715 requires storing information in |
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* the bottom 3 bits of the stack pointer. Add a padding field to |
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* force the size of the struct to be a multiple of 8. |
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*/ |
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u_register_t pad; |
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} smc_ctx_t __aligned(8); |
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|
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/*
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* Compile time assertions related to the 'smc_context' structure to |
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* ensure that the assembler and the compiler view of the offsets of |
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* the structure members is the same. |
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*/ |
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CASSERT(SMC_CTX_GPREG_R0 == __builtin_offsetof(smc_ctx_t, r0), \ |
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assert_smc_ctx_greg_r0_offset_mismatch); |
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CASSERT(SMC_CTX_GPREG_R1 == __builtin_offsetof(smc_ctx_t, r1), \ |
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assert_smc_ctx_greg_r1_offset_mismatch); |
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CASSERT(SMC_CTX_GPREG_R2 == __builtin_offsetof(smc_ctx_t, r2), \ |
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assert_smc_ctx_greg_r2_offset_mismatch); |
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CASSERT(SMC_CTX_GPREG_R3 == __builtin_offsetof(smc_ctx_t, r3), \ |
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assert_smc_ctx_greg_r3_offset_mismatch); |
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CASSERT(SMC_CTX_GPREG_R4 == __builtin_offsetof(smc_ctx_t, r4), \ |
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assert_smc_ctx_greg_r4_offset_mismatch); |
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CASSERT(SMC_CTX_SP_USR == __builtin_offsetof(smc_ctx_t, sp_usr), \ |
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assert_smc_ctx_sp_usr_offset_mismatch); |
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CASSERT(SMC_CTX_LR_MON == __builtin_offsetof(smc_ctx_t, lr_mon), \ |
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assert_smc_ctx_lr_mon_offset_mismatch); |
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CASSERT(SMC_CTX_SPSR_MON == __builtin_offsetof(smc_ctx_t, spsr_mon), \ |
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assert_smc_ctx_spsr_mon_offset_mismatch); |
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|
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CASSERT((sizeof(smc_ctx_t) & 0x7) == 0, assert_smc_ctx_not_aligned); |
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CASSERT(SMC_CTX_SIZE == sizeof(smc_ctx_t), assert_smc_ctx_size_mismatch); |
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|
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/* Convenience macros to return from SMC handler */ |
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#define SMC_RET0(_h) { \ |
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return (uintptr_t)(_h); \ |
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} |
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#define SMC_RET1(_h, _r0) { \ |
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((smc_ctx_t *)(_h))->r0 = (_r0); \ |
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SMC_RET0(_h); \ |
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} |
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#define SMC_RET2(_h, _r0, _r1) { \ |
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((smc_ctx_t *)(_h))->r1 = (_r1); \ |
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SMC_RET1(_h, (_r0)); \ |
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} |
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#define SMC_RET3(_h, _r0, _r1, _r2) { \ |
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((smc_ctx_t *)(_h))->r2 = (_r2); \ |
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SMC_RET2(_h, (_r0), (_r1)); \ |
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} |
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#define SMC_RET4(_h, _r0, _r1, _r2, _r3) { \ |
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((smc_ctx_t *)(_h))->r3 = (_r3); \ |
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SMC_RET3(_h, (_r0), (_r1), (_r2)); \ |
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} |
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|
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/* Return a UUID in the SMC return registers */ |
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#define SMC_UUID_RET(_h, _uuid) \ |
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SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ |
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((const uint32_t *) &(_uuid))[1], \ |
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((const uint32_t *) &(_uuid))[2], \ |
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((const uint32_t *) &(_uuid))[3]) |
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|
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/*
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* Helper macro to retrieve the SMC parameters from smc_ctx_t. |
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*/ |
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#define get_smc_params_from_ctx(_hdl, _r1, _r2, _r3, _r4) { \ |
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_r1 = ((smc_ctx_t *)_hdl)->r1; \ |
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_r2 = ((smc_ctx_t *)_hdl)->r2; \ |
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_r3 = ((smc_ctx_t *)_hdl)->r3; \ |
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_r4 = ((smc_ctx_t *)_hdl)->r4; \ |
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} |
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|
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/* ------------------------------------------------------------------------
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* Helper APIs for setting and retrieving appropriate `smc_ctx_t`. |
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* These functions need to implemented by the BL including this library. |
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* ------------------------------------------------------------------------ |
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*/ |
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|
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/* Get the pointer to `smc_ctx_t` corresponding to the security state. */ |
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void *smc_get_ctx(unsigned int security_state); |
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|
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/* Set the next `smc_ctx_t` corresponding to the security state. */ |
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void smc_set_next_ctx(unsigned int security_state); |
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|
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/* Get the pointer to next `smc_ctx_t` already set by `smc_set_next_ctx()`. */ |
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void *smc_get_next_ctx(void); |
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|
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#endif /*__ASSEMBLY__*/ |
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|
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#endif /* __SMCCC_HELPERS_H__ */ |
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@ -0,0 +1,199 @@ |
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/* |
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __SMCCC_MACROS_S__ |
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#define __SMCCC_MACROS_S__ |
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|
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#include <arch.h> |
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|
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/* |
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* Macro to save the General purpose registers (r0 - r12), the banked |
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* spsr, lr, sp registers and the `scr` register to the SMC context on entry |
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* due a SMC call. The `lr` of the current mode (monitor) is expected to be |
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* already saved. The `sp` must point to the `smc_ctx_t` to save to. |
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* Additionally, also save the 'pmcr' register as this is updated whilst |
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* executing in the secure world. |
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*/ |
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.macro smccc_save_gp_mode_regs |
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/* Save r0 - r12 in the SMC context */ |
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stm sp, {r0-r12} |
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mov r0, sp |
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add r0, r0, #SMC_CTX_SP_USR |
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|
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#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) |
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/* Must be in secure state to restore Monitor mode */ |
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ldcopr r4, SCR |
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bic r2, r4, #SCR_NS_BIT |
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stcopr r2, SCR |
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isb |
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|
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cps #MODE32_sys |
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stm r0!, {sp, lr} |
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|
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cps #MODE32_irq |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_fiq |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_svc |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_abt |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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cps #MODE32_und |
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mrs r2, spsr |
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stm r0!, {r2, sp, lr} |
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|
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/* lr_mon is already saved by caller */ |
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cps #MODE32_mon |
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mrs r2, spsr |
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stm r0!, {r2} |
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|
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stcopr r4, SCR |
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isb |
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#else |
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/* Save the banked registers including the current SPSR and LR */ |
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mrs r4, sp_usr |
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mrs r5, lr_usr |
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mrs r6, spsr_irq |
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mrs r7, sp_irq |
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mrs r8, lr_irq |
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mrs r9, spsr_fiq |
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mrs r10, sp_fiq |
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mrs r11, lr_fiq |
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mrs r12, spsr_svc |
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stm r0!, {r4-r12} |
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|
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mrs r4, sp_svc |
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mrs r5, lr_svc |
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mrs r6, spsr_abt |
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mrs r7, sp_abt |
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mrs r8, lr_abt |
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mrs r9, spsr_und |
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mrs r10, sp_und |
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mrs r11, lr_und |
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mrs r12, spsr |
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stm r0!, {r4-r12} |
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/* lr_mon is already saved by caller */ |
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|
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ldcopr r4, SCR |
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#endif |
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str r4, [sp, #SMC_CTX_SCR] |
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ldcopr r4, PMCR |
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str r4, [sp, #SMC_CTX_PMCR] |
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.endm |
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|
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/* |
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* Macro to restore the `smc_ctx_t`, which includes the General purpose |
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* registers and banked mode registers, and exit from the monitor mode. |
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* r0 must point to the `smc_ctx_t` to restore from. |
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*/ |
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.macro monitor_exit |
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/* |
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* Save the current sp and restore the smc context |
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* pointer to sp which will be used for handling the |
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* next SMC. |
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*/ |
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str sp, [r0, #SMC_CTX_SP_MON] |
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mov sp, r0 |
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|
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/* |
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* Restore SCR first so that we access the right banked register |
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* when the other mode registers are restored. |
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*/ |
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ldr r1, [r0, #SMC_CTX_SCR] |
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stcopr r1, SCR |
|||
isb |
|||
|
|||
/* |
|||
* Restore the PMCR register. |
|||
*/ |
|||
ldr r1, [r0, #SMC_CTX_PMCR] |
|||
stcopr r1, PMCR |
|||
|
|||
/* Restore the banked registers including the current SPSR */ |
|||
add r1, r0, #SMC_CTX_SP_USR |
|||
|
|||
#if ARM_ARCH_MAJOR == 7 && !defined(ARMV7_SUPPORTS_VIRTUALIZATION) |
|||
/* Must be in secure state to restore Monitor mode */ |
|||
ldcopr r4, SCR |
|||
bic r2, r4, #SCR_NS_BIT |
|||
stcopr r2, SCR |
|||
isb |
|||
|
|||
cps #MODE32_sys |
|||
ldm r1!, {sp, lr} |
|||
|
|||
cps #MODE32_irq |
|||
ldm r1!, {r2, sp, lr} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
cps #MODE32_fiq |
|||
ldm r1!, {r2, sp, lr} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
cps #MODE32_svc |
|||
ldm r1!, {r2, sp, lr} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
cps #MODE32_abt |
|||
ldm r1!, {r2, sp, lr} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
cps #MODE32_und |
|||
ldm r1!, {r2, sp, lr} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
cps #MODE32_mon |
|||
ldm r1!, {r2} |
|||
msr spsr_fsxc, r2 |
|||
|
|||
stcopr r4, SCR |
|||
isb |
|||
#else |
|||
ldm r1!, {r4-r12} |
|||
msr sp_usr, r4 |
|||
msr lr_usr, r5 |
|||
msr spsr_irq, r6 |
|||
msr sp_irq, r7 |
|||
msr lr_irq, r8 |
|||
msr spsr_fiq, r9 |
|||
msr sp_fiq, r10 |
|||
msr lr_fiq, r11 |
|||
msr spsr_svc, r12 |
|||
|
|||
ldm r1!, {r4-r12} |
|||
msr sp_svc, r4 |
|||
msr lr_svc, r5 |
|||
msr spsr_abt, r6 |
|||
msr sp_abt, r7 |
|||
msr lr_abt, r8 |
|||
msr spsr_und, r9 |
|||
msr sp_und, r10 |
|||
msr lr_und, r11 |
|||
/* |
|||
* Use the `_fsxc` suffix explicitly to instruct the assembler |
|||
* to update all the 32 bits of SPSR. Else, by default, the |
|||
* assembler assumes `_fc` suffix which only modifies |
|||
* f->[31:24] and c->[7:0] bits of SPSR. |
|||
*/ |
|||
msr spsr_fsxc, r12 |
|||
#endif |
|||
|
|||
/* Restore the LR */ |
|||
ldr lr, [r0, #SMC_CTX_LR_MON] |
|||
|
|||
/* Restore the rest of the general purpose registers */ |
|||
ldm r0, {r0-r12} |
|||
eret |
|||
.endm |
|||
|
|||
#endif /* __SMCCC_MACROS_S__ */ |
|||
@ -0,0 +1,91 @@ |
|||
/*
|
|||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#ifndef __SMCCC_HELPERS_H__ |
|||
#define __SMCCC_HELPERS_H__ |
|||
|
|||
#include <smccc.h> |
|||
|
|||
#ifndef __ASSEMBLY__ |
|||
#include <context.h> |
|||
|
|||
/* Convenience macros to return from SMC handler */ |
|||
#define SMC_RET0(_h) { \ |
|||
return (uint64_t) (_h); \ |
|||
} |
|||
#define SMC_RET1(_h, _x0) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X0), (_x0)); \ |
|||
SMC_RET0(_h); \ |
|||
} |
|||
#define SMC_RET2(_h, _x0, _x1) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X1), (_x1)); \ |
|||
SMC_RET1(_h, (_x0)); \ |
|||
} |
|||
#define SMC_RET3(_h, _x0, _x1, _x2) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X2), (_x2)); \ |
|||
SMC_RET2(_h, (_x0), (_x1)); \ |
|||
} |
|||
#define SMC_RET4(_h, _x0, _x1, _x2, _x3) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X3), (_x3)); \ |
|||
SMC_RET3(_h, (_x0), (_x1), (_x2)); \ |
|||
} |
|||
#define SMC_RET5(_h, _x0, _x1, _x2, _x3, _x4) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X4), (_x4)); \ |
|||
SMC_RET4(_h, (_x0), (_x1), (_x2), (_x3)); \ |
|||
} |
|||
#define SMC_RET6(_h, _x0, _x1, _x2, _x3, _x4, _x5) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \ |
|||
SMC_RET5(_h, (_x0), (_x1), (_x2), (_x3), (_x4)); \ |
|||
} |
|||
#define SMC_RET7(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X6), (_x6)); \ |
|||
SMC_RET6(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5)); \ |
|||
} |
|||
#define SMC_RET8(_h, _x0, _x1, _x2, _x3, _x4, _x5, _x6, _x7) { \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X7), (_x7)); \ |
|||
SMC_RET7(_h, (_x0), (_x1), (_x2), (_x3), (_x4), (_x5), (_x6)); \ |
|||
} |
|||
|
|||
/*
|
|||
* Convenience macros to access general purpose registers using handle provided |
|||
* to SMC handler. These take the offset values defined in context.h |
|||
*/ |
|||
#define SMC_GET_GP(_h, _g) \ |
|||
read_ctx_reg((get_gpregs_ctx(_h)), (_g)) |
|||
#define SMC_SET_GP(_h, _g, _v) \ |
|||
write_ctx_reg((get_gpregs_ctx(_h)), (_g), (_v)) |
|||
|
|||
/*
|
|||
* Convenience macros to access EL3 context registers using handle provided to |
|||
* SMC handler. These take the offset values defined in context.h |
|||
*/ |
|||
#define SMC_GET_EL3(_h, _e) \ |
|||
read_ctx_reg((get_el3state_ctx(_h)), (_e)) |
|||
#define SMC_SET_EL3(_h, _e, _v) \ |
|||
write_ctx_reg((get_el3state_ctx(_h)), (_e), (_v)) |
|||
|
|||
/* Return a UUID in the SMC return registers */ |
|||
#define SMC_UUID_RET(_h, _uuid) \ |
|||
SMC_RET4(handle, ((const uint32_t *) &(_uuid))[0], \ |
|||
((const uint32_t *) &(_uuid))[1], \ |
|||
((const uint32_t *) &(_uuid))[2], \ |
|||
((const uint32_t *) &(_uuid))[3]) |
|||
|
|||
/*
|
|||
* Helper macro to retrieve the SMC parameters from cpu_context_t. |
|||
*/ |
|||
#define get_smc_params_from_ctx(_hdl, _x1, _x2, _x3, _x4) \ |
|||
do { \ |
|||
const gp_regs_t *regs = get_gpregs_ctx(_hdl); \ |
|||
_x1 = read_ctx_reg(regs, CTX_GPREG_X1); \ |
|||
_x2 = read_ctx_reg(regs, CTX_GPREG_X2); \ |
|||
_x3 = read_ctx_reg(regs, CTX_GPREG_X3); \ |
|||
_x4 = read_ctx_reg(regs, CTX_GPREG_X4); \ |
|||
} while (0) |
|||
|
|||
#endif /*__ASSEMBLY__*/ |
|||
|
|||
#endif /* __SMCCC_HELPERS_H__ */ |
|||
@ -0,0 +1,109 @@ |
|||
/*
|
|||
* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
|||
* |
|||
* SPDX-License-Identifier: BSD-3-Clause |
|||
*/ |
|||
|
|||
#ifndef __SMCCC_H__ |
|||
#define __SMCCC_H__ |
|||
|
|||
#include <utils_def.h> |
|||
|
|||
/*******************************************************************************
|
|||
* Bit definitions inside the function id as per the SMC calling convention |
|||
******************************************************************************/ |
|||
#define FUNCID_TYPE_SHIFT U(31) |
|||
#define FUNCID_CC_SHIFT U(30) |
|||
#define FUNCID_OEN_SHIFT U(24) |
|||
#define FUNCID_NUM_SHIFT U(0) |
|||
|
|||
#define FUNCID_TYPE_MASK U(0x1) |
|||
#define FUNCID_CC_MASK U(0x1) |
|||
#define FUNCID_OEN_MASK U(0x3f) |
|||
#define FUNCID_NUM_MASK U(0xffff) |
|||
|
|||
#define FUNCID_TYPE_WIDTH U(1) |
|||
#define FUNCID_CC_WIDTH U(1) |
|||
#define FUNCID_OEN_WIDTH U(6) |
|||
#define FUNCID_NUM_WIDTH U(16) |
|||
|
|||
#define GET_SMC_CC(id) ((id >> FUNCID_CC_SHIFT) & \ |
|||
FUNCID_CC_MASK) |
|||
#define GET_SMC_TYPE(id) ((id >> FUNCID_TYPE_SHIFT) & \ |
|||
FUNCID_TYPE_MASK) |
|||
|
|||
#define SMC_64 U(1) |
|||
#define SMC_32 U(0) |
|||
#define SMC_OK U(0) |
|||
#define SMC_UNK -1 |
|||
#define SMC_TYPE_FAST ULL(1) |
|||
#if !ERROR_DEPRECATED |
|||
#define SMC_TYPE_STD ULL(0) |
|||
#endif |
|||
#define SMC_TYPE_YIELD U(0) |
|||
#define SMC_PREEMPTED -2 |
|||
/*******************************************************************************
|
|||
* Owning entity number definitions inside the function id as per the SMC |
|||
* calling convention |
|||
******************************************************************************/ |
|||
#define OEN_ARM_START U(0) |
|||
#define OEN_ARM_END U(0) |
|||
#define OEN_CPU_START U(1) |
|||
#define OEN_CPU_END U(1) |
|||
#define OEN_SIP_START U(2) |
|||
#define OEN_SIP_END U(2) |
|||
#define OEN_OEM_START U(3) |
|||
#define OEN_OEM_END U(3) |
|||
#define OEN_STD_START U(4) /* Standard Service Calls */ |
|||
#define OEN_STD_END U(4) |
|||
#define OEN_TAP_START U(48) /* Trusted Applications */ |
|||
#define OEN_TAP_END U(49) |
|||
#define OEN_TOS_START U(50) /* Trusted OS */ |
|||
#define OEN_TOS_END U(63) |
|||
#define OEN_LIMIT U(64) |
|||
|
|||
#ifndef __ASSEMBLY__ |
|||
|
|||
#include <cassert.h> |
|||
#include <stdint.h> |
|||
|
|||
#define SMCCC_MAJOR_VERSION U(1) |
|||
#define SMCCC_MINOR_VERSION U(1) |
|||
|
|||
#define MAKE_SMCCC_VERSION(_major, _minor) (((_major) << 16) | (_minor)) |
|||
|
|||
/* Various flags passed to SMC handlers */ |
|||
#define SMC_FROM_SECURE (U(0) << 0) |
|||
#define SMC_FROM_NON_SECURE (U(1) << 0) |
|||
|
|||
#define is_caller_non_secure(_f) (!!(_f & SMC_FROM_NON_SECURE)) |
|||
#define is_caller_secure(_f) (!(is_caller_non_secure(_f))) |
|||
|
|||
/* The macro below is used to identify a Standard Service SMC call */ |
|||
#define is_std_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ |
|||
FUNCID_OEN_MASK) == OEN_STD_START) |
|||
|
|||
/* The macro below is used to identify a Arm Architectural Service SMC call */ |
|||
#define is_arm_arch_svc_call(_fid) ((((_fid) >> FUNCID_OEN_SHIFT) & \ |
|||
FUNCID_OEN_MASK) == OEN_ARM_START) |
|||
|
|||
/* The macro below is used to identify a valid Fast SMC call */ |
|||
#define is_valid_fast_smc(_fid) ((!(((_fid) >> 16) & U(0xff))) && \ |
|||
(GET_SMC_TYPE(_fid) == SMC_TYPE_FAST)) |
|||
|
|||
/*
|
|||
* Macro to define UUID for services. Apart from defining and initializing a |
|||
* uuid_t structure, this macro verifies that the first word of the defined UUID |
|||
* does not equal SMC_UNK. This is to ensure that the caller won't mistake the |
|||
* returned UUID in x0 for an invalid SMC error return |
|||
*/ |
|||
#define DEFINE_SVC_UUID(_name, _tl, _tm, _th, _cl, _ch, \ |
|||
_n0, _n1, _n2, _n3, _n4, _n5) \ |
|||
CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\ |
|||
static const uuid_t _name = { \ |
|||
_tl, _tm, _th, _cl, _ch, \ |
|||
{ _n0, _n1, _n2, _n3, _n4, _n5 } \ |
|||
} |
|||
|
|||
#endif /*__ASSEMBLY__*/ |
|||
#endif /* __SMCCC_H__ */ |
|||
Loading…
Reference in new issue