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refactor(fvp): fdts: merge motherboard .dtsi files 

For no real reason we were shipping two separate DT include files for the
base FVP motherboard peripherals, one for aarch32, one for aarch64.
There is no difference in the hardware description when using a
different instruction set, and the diff between the two files was about
a missing interrupt map for the 64-bit DT files.

Consolidate the situation by just using a single motherboard .dtsi file,
which relies on an interrupt map by the including files.
Provide that map in the two files where it was missing before, and
change the filenames to let all users include the same file now.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: I19b77ecc8da9b4bfbd61d02f910b9ab05dbf92e9
pull/1988/merge
Andre Przywara 2 years ago
parent
a25349b75c
commit
08f3c2bcdd
7 changed files with 116 additions and 23 deletions
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  1. 2
      fdts/fvp-base-gicv2-psci-aarch32.dts
  2. 46
      fdts/fvp-base-gicv2-psci.dts
  3. 2
      fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
  4. 55
      fdts/fvp-base-gicv3-psci-common.dtsi
  5. 2
      fdts/fvp-ve-Cortex-A5x1.dts
  6. 2
      fdts/fvp-ve-Cortex-A7x1.dts
  7. 30
      fdts/rtsm_ve-motherboard.dtsi

2
fdts/fvp-base-gicv2-psci-aarch32.dts
View File

@ -187,7 +187,7 @@
<0 0 41 &gic 0 41 4>, <0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>; <0 0 42 &gic 0 42 4>;
#include "rtsm_ve-motherboard-aarch32.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };
panels { panels {

46
fdts/fvp-base-gicv2-psci.dts
View File

@ -140,6 +140,52 @@
<4 0 0 0x0c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>; <5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 0 4>,
<0 0 1 &gic 0 1 4>,
<0 0 2 &gic 0 2 4>,
<0 0 3 &gic 0 3 4>,
<0 0 4 &gic 0 4 4>,
<0 0 5 &gic 0 5 4>,
<0 0 6 &gic 0 6 4>,
<0 0 7 &gic 0 7 4>,
<0 0 8 &gic 0 8 4>,
<0 0 9 &gic 0 9 4>,
<0 0 10 &gic 0 10 4>,
<0 0 11 &gic 0 11 4>,
<0 0 12 &gic 0 12 4>,
<0 0 13 &gic 0 13 4>,
<0 0 14 &gic 0 14 4>,
<0 0 15 &gic 0 15 4>,
<0 0 16 &gic 0 16 4>,
<0 0 17 &gic 0 17 4>,
<0 0 18 &gic 0 18 4>,
<0 0 19 &gic 0 19 4>,
<0 0 20 &gic 0 20 4>,
<0 0 21 &gic 0 21 4>,
<0 0 22 &gic 0 22 4>,
<0 0 23 &gic 0 23 4>,
<0 0 24 &gic 0 24 4>,
<0 0 25 &gic 0 25 4>,
<0 0 26 &gic 0 26 4>,
<0 0 27 &gic 0 27 4>,
<0 0 28 &gic 0 28 4>,
<0 0 29 &gic 0 29 4>,
<0 0 30 &gic 0 30 4>,
<0 0 31 &gic 0 31 4>,
<0 0 32 &gic 0 32 4>,
<0 0 33 &gic 0 33 4>,
<0 0 34 &gic 0 34 4>,
<0 0 35 &gic 0 35 4>,
<0 0 36 &gic 0 36 4>,
<0 0 37 &gic 0 37 4>,
<0 0 38 &gic 0 38 4>,
<0 0 39 &gic 0 39 4>,
<0 0 40 &gic 0 40 4>,
<0 0 41 &gic 0 41 4>,
<0 0 42 &gic 0 42 4>;
#include "rtsm_ve-motherboard.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };

2
fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
View File

@ -188,7 +188,7 @@
<0 0 41 &gic 0 0 0 41 4>, <0 0 41 &gic 0 0 0 41 4>,
<0 0 42 &gic 0 0 0 42 4>; <0 0 42 &gic 0 0 0 42 4>;
#include "rtsm_ve-motherboard-aarch32.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };
panels { panels {

55
fdts/fvp-base-gicv3-psci-common.dtsi
View File

@ -146,9 +146,9 @@
gic: interrupt-controller@2f000000 { gic: interrupt-controller@2f000000 {
compatible = "arm,gic-v3"; compatible = "arm,gic-v3";
#interrupt-cells = <3>; #interrupt-cells = <3>;
#address-cells = <2>; #address-cells = <1>;
#size-cells = <2>; #size-cells = <1>;
ranges; ranges = <0x0 0x0 0x2f000000 0x100000>;
interrupt-controller; interrupt-controller;
reg = <0x0 0x2f000000 0 0x10000>, // GICD reg = <0x0 0x2f000000 0 0x10000>, // GICD
<0x0 0x2f100000 0 0x200000>, // GICR <0x0 0x2f100000 0 0x200000>, // GICR
@ -160,7 +160,8 @@
its: its@2f020000 { its: its@2f020000 {
compatible = "arm,gic-v3-its"; compatible = "arm,gic-v3-its";
msi-controller; msi-controller;
reg = <0x0 0x2f020000 0x0 0x20000>; // GITS #msi-cells = <1>;
reg = <0x20000 0x20000>; // GITS
}; };
}; };
@ -211,6 +212,52 @@
<4 0 0 0x0c000000 0x04000000>, <4 0 0 0x0c000000 0x04000000>,
<5 0 0 0x10000000 0x04000000>; <5 0 0 0x10000000 0x04000000>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 63>;
interrupt-map = <0 0 0 &gic 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<0 0 1 &gic 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<0 0 2 &gic 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<0 0 3 &gic 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<0 0 4 &gic 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<0 0 5 &gic 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<0 0 6 &gic 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<0 0 7 &gic 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<0 0 8 &gic 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<0 0 9 &gic 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<0 0 10 &gic 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<0 0 11 &gic 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<0 0 12 &gic 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<0 0 13 &gic 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<0 0 14 &gic 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<0 0 15 &gic 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<0 0 16 &gic 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<0 0 17 &gic 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<0 0 18 &gic 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<0 0 19 &gic 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<0 0 20 &gic 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<0 0 21 &gic 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<0 0 22 &gic 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<0 0 23 &gic 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<0 0 24 &gic 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<0 0 25 &gic 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<0 0 26 &gic 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<0 0 27 &gic 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<0 0 28 &gic 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<0 0 29 &gic 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<0 0 30 &gic 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<0 0 31 &gic 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<0 0 32 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<0 0 33 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<0 0 34 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<0 0 35 &gic 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<0 0 36 &gic 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<0 0 37 &gic 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<0 0 38 &gic 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<0 0 39 &gic 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<0 0 40 &gic 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<0 0 41 &gic 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<0 0 42 &gic 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#include "rtsm_ve-motherboard.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };

2
fdts/fvp-ve-Cortex-A5x1.dts
View File

@ -153,6 +153,6 @@
<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#include "rtsm_ve-motherboard-aarch32.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };
}; };

2
fdts/fvp-ve-Cortex-A7x1.dts
View File

@ -85,6 +85,6 @@
<0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, <0 0 44 &gic GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; <0 0 46 &gic GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
#include "rtsm_ve-motherboard-aarch32.dtsi" #include "rtsm_ve-motherboard.dtsi"
}; };
}; };

30
fdts/rtsm_ve-motherboard.dtsi
View File

@ -26,7 +26,7 @@
ethernet@2,02000000 { ethernet@2,02000000 {
compatible = "smsc,lan91c111"; compatible = "smsc,lan91c111";
reg = <2 0x02000000 0x10000>; reg = <2 0x02000000 0x10000>;
interrupts = <0 15 4>; interrupts = <15>;
}; };
v2m_clk24mhz: clk24mhz { v2m_clk24mhz: clk24mhz {
@ -75,7 +75,7 @@
aaci@40000 { aaci@40000 {
compatible = "arm,pl041", "arm,primecell"; compatible = "arm,pl041", "arm,primecell";
reg = <0x040000 0x1000>; reg = <0x040000 0x1000>;
interrupts = <0 11 4>; interrupts = <11>;
clocks = <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
}; };
@ -83,7 +83,7 @@
mmci@50000 { mmci@50000 {
compatible = "arm,pl180", "arm,primecell"; compatible = "arm,pl180", "arm,primecell";
reg = <0x050000 0x1000>; reg = <0x050000 0x1000>;
interrupts = <0 9 4 0 10 4>; interrupts = <9>, <10>;
cd-gpios = <&v2m_sysreg 0 0>; cd-gpios = <&v2m_sysreg 0 0>;
wp-gpios = <&v2m_sysreg 1 0>; wp-gpios = <&v2m_sysreg 1 0>;
max-frequency = <12000000>; max-frequency = <12000000>;
@ -95,7 +95,7 @@
kmi@60000 { kmi@60000 {
compatible = "arm,pl050", "arm,primecell"; compatible = "arm,pl050", "arm,primecell";
reg = <0x060000 0x1000>; reg = <0x060000 0x1000>;
interrupts = <0 12 4>; interrupts = <12>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk"; clock-names = "KMIREFCLK", "apb_pclk";
}; };
@ -103,7 +103,7 @@
kmi@70000 { kmi@70000 {
compatible = "arm,pl050", "arm,primecell"; compatible = "arm,pl050", "arm,primecell";
reg = <0x070000 0x1000>; reg = <0x070000 0x1000>;
interrupts = <0 13 4>; interrupts = <13>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "KMIREFCLK", "apb_pclk"; clock-names = "KMIREFCLK", "apb_pclk";
}; };
@ -111,7 +111,7 @@
v2m_serial0: uart@90000 { v2m_serial0: uart@90000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0x090000 0x1000>; reg = <0x090000 0x1000>;
interrupts = <0 5 4>; interrupts = <5>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk"; clock-names = "uartclk", "apb_pclk";
}; };
@ -119,7 +119,7 @@
v2m_serial1: uart@a0000 { v2m_serial1: uart@a0000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0x0a0000 0x1000>; reg = <0x0a0000 0x1000>;
interrupts = <0 6 4>; interrupts = <6>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk"; clock-names = "uartclk", "apb_pclk";
}; };
@ -127,7 +127,7 @@
v2m_serial2: uart@b0000 { v2m_serial2: uart@b0000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0x0b0000 0x1000>; reg = <0x0b0000 0x1000>;
interrupts = <0 7 4>; interrupts = <7>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk"; clock-names = "uartclk", "apb_pclk";
}; };
@ -135,7 +135,7 @@
v2m_serial3: uart@c0000 { v2m_serial3: uart@c0000 {
compatible = "arm,pl011", "arm,primecell"; compatible = "arm,pl011", "arm,primecell";
reg = <0x0c0000 0x1000>; reg = <0x0c0000 0x1000>;
interrupts = <0 8 4>; interrupts = <8>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "uartclk", "apb_pclk"; clock-names = "uartclk", "apb_pclk";
}; };
@ -143,7 +143,7 @@
wdt@f0000 { wdt@f0000 {
compatible = "arm,sp805", "arm,primecell"; compatible = "arm,sp805", "arm,primecell";
reg = <0x0f0000 0x1000>; reg = <0x0f0000 0x1000>;
interrupts = <0 0 4>; interrupts = <0>;
clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
clock-names = "wdogclk", "apb_pclk"; clock-names = "wdogclk", "apb_pclk";
}; };
@ -151,7 +151,7 @@
v2m_timer01: timer@110000 { v2m_timer01: timer@110000 {
compatible = "arm,sp804", "arm,primecell"; compatible = "arm,sp804", "arm,primecell";
reg = <0x110000 0x1000>; reg = <0x110000 0x1000>;
interrupts = <0 2 4>; interrupts = <2>;
clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk"; clock-names = "timclken1", "timclken2", "apb_pclk";
}; };
@ -159,7 +159,7 @@
v2m_timer23: timer@120000 { v2m_timer23: timer@120000 {
compatible = "arm,sp804", "arm,primecell"; compatible = "arm,sp804", "arm,primecell";
reg = <0x120000 0x1000>; reg = <0x120000 0x1000>;
interrupts = <0 3 4>; interrupts = <3>;
clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
clock-names = "timclken1", "timclken2", "apb_pclk"; clock-names = "timclken1", "timclken2", "apb_pclk";
}; };
@ -167,7 +167,7 @@
rtc@170000 { rtc@170000 {
compatible = "arm,pl031", "arm,primecell"; compatible = "arm,pl031", "arm,primecell";
reg = <0x170000 0x1000>; reg = <0x170000 0x1000>;
interrupts = <0 4 4>; interrupts = <4>;
clocks = <&v2m_clk24mhz>; clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
}; };
@ -175,7 +175,7 @@
clcd@1f0000 { clcd@1f0000 {
compatible = "arm,pl111", "arm,primecell"; compatible = "arm,pl111", "arm,primecell";
reg = <0x1f0000 0x1000>; reg = <0x1f0000 0x1000>;
interrupts = <0 14 4>; interrupts = <14>;
clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>;
clock-names = "clcdclk", "apb_pclk"; clock-names = "clcdclk", "apb_pclk";
mode = "XVGA"; mode = "XVGA";
@ -186,7 +186,7 @@
virtio_block@130000 { virtio_block@130000 {
compatible = "virtio,mmio"; compatible = "virtio,mmio";
reg = <0x130000 0x1000>; reg = <0x130000 0x1000>;
interrupts = <0 0x2a 4>; interrupts = <0x2a>;
}; };
}; };

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