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@ -1,5 +1,5 @@ |
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/*
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* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. |
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* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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@ -47,6 +47,7 @@ uintptr_t fip_dev_handle; |
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uintptr_t storage_dev_handle; |
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static const io_dev_connector_t *fip_dev_con; |
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static uint32_t nand_block_sz __maybe_unused; |
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#ifndef DECRYPTION_SUPPORT_none |
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static const io_dev_connector_t *enc_dev_con; |
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@ -310,11 +311,55 @@ static void boot_spi_nor(boot_api_context_t *boot_context) |
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} |
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#endif /* STM32MP_SPI_NOR */ |
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#if STM32MP_RAW_NAND || STM32MP_SPI_NAND |
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/*
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* This function returns 0 if it can find an alternate |
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* image to be loaded or a negative errno otherwise. |
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*/ |
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static int try_nand_backup_partitions(unsigned int image_id) |
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{ |
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static unsigned int backup_id; |
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static unsigned int backup_block_nb; |
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/* Check if NAND storage used */ |
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if (nand_block_sz == 0U) { |
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return -ENODEV; |
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} |
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if (backup_id != image_id) { |
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backup_block_nb = PLATFORM_MTD_MAX_PART_SIZE / nand_block_sz; |
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backup_id = image_id; |
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} |
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if (backup_block_nb-- == 0U) { |
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return -ENOSPC; |
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} |
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#if PSA_FWU_SUPPORT |
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if (((image_block_spec.offset < STM32MP_NAND_FIP_B_OFFSET) && |
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((image_block_spec.offset + nand_block_sz) >= STM32MP_NAND_FIP_B_OFFSET)) || |
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(image_block_spec.offset + nand_block_sz >= STM32MP_NAND_FIP_B_MAX_OFFSET)) { |
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return 0; |
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} |
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#endif |
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image_block_spec.offset += nand_block_sz; |
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return 0; |
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} |
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static const struct plat_try_images_ops try_img_ops = { |
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.next_instance = try_nand_backup_partitions, |
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}; |
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#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ |
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#if STM32MP_RAW_NAND |
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static void boot_fmc2_nand(boot_api_context_t *boot_context) |
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{ |
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int io_result __maybe_unused; |
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plat_setup_try_img_ops(&try_img_ops); |
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io_result = stm32_fmc2_init(); |
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assert(io_result == 0); |
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@ -326,6 +371,8 @@ static void boot_fmc2_nand(boot_api_context_t *boot_context) |
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io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, |
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&storage_dev_handle); |
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assert(io_result == 0); |
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nand_block_sz = nand_dev_spec.erase_size; |
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} |
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#endif /* STM32MP_RAW_NAND */ |
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@ -334,6 +381,8 @@ static void boot_spi_nand(boot_api_context_t *boot_context) |
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{ |
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int io_result __maybe_unused; |
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plat_setup_try_img_ops(&try_img_ops); |
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io_result = stm32_qspi_init(); |
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assert(io_result == 0); |
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@ -345,6 +394,8 @@ static void boot_spi_nand(boot_api_context_t *boot_context) |
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(uintptr_t)&spi_nand_dev_spec, |
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&storage_dev_handle); |
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assert(io_result == 0); |
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nand_block_sz = spi_nand_dev_spec.erase_size; |
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} |
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#endif /* STM32MP_SPI_NAND */ |
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@ -530,7 +581,14 @@ int bl2_plat_handle_pre_image_load(unsigned int image_id) |
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#if STM32MP_SPI_NAND |
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: |
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#endif |
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/*
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* With FWU Multi Bank feature enabled, the selection of |
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* the image to boot will be done by fwu_init calling the |
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* platform hook, plat_fwu_set_images_source. |
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*/ |
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#if !PSA_FWU_SUPPORT |
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image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; |
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#endif |
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break; |
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#endif |
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@ -596,7 +654,7 @@ int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, |
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return rc; |
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} |
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#if (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT |
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#if PSA_FWU_SUPPORT |
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/*
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* In each boot in non-trial mode, we set the BKP register to |
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* FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata. |
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@ -709,6 +767,19 @@ void plat_fwu_set_images_source(const struct fwu_metadata *metadata) |
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panic(); |
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} |
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break; |
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#endif |
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#if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) |
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: |
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: |
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if (guidcmp(img_guid, &STM32MP_NAND_FIP_A_GUID) == 0) { |
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image_spec->offset = STM32MP_NAND_FIP_A_OFFSET; |
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} else if (guidcmp(img_guid, &STM32MP_NAND_FIP_B_GUID) == 0) { |
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image_spec->offset = STM32MP_NAND_FIP_B_OFFSET; |
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} else { |
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ERROR("Invalid uuid mentioned in metadata\n"); |
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panic(); |
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} |
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break; |
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#endif |
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default: |
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panic(); |
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@ -717,9 +788,9 @@ void plat_fwu_set_images_source(const struct fwu_metadata *metadata) |
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} |
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} |
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static int plat_set_image_source(unsigned int image_id, |
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uintptr_t *handle, |
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uintptr_t *image_spec) |
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static int set_metadata_image_source(unsigned int image_id, |
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uintptr_t *handle, |
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uintptr_t *image_spec) |
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{ |
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struct plat_io_policy *policy; |
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io_block_spec_t *spec __maybe_unused; |
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@ -762,6 +833,19 @@ static int plat_set_image_source(unsigned int image_id, |
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spec->length = sizeof(struct fwu_metadata); |
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break; |
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#endif |
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#if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) |
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: |
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case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: |
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if (image_id == FWU_METADATA_IMAGE_ID) { |
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spec->offset = STM32MP_NAND_METADATA1_OFFSET; |
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} else { |
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spec->offset = STM32MP_NAND_METADATA2_OFFSET; |
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} |
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spec->length = sizeof(struct fwu_metadata); |
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break; |
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#endif |
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default: |
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panic(); |
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break; |
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@ -780,6 +864,6 @@ int plat_fwu_set_metadata_image_source(unsigned int image_id, |
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assert((image_id == FWU_METADATA_IMAGE_ID) || |
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(image_id == BKUP_FWU_METADATA_IMAGE_ID)); |
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return plat_set_image_source(image_id, handle, image_spec); |
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return set_metadata_image_source(image_id, handle, image_spec); |
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} |
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#endif /* (STM32MP_SDMMC || STM32MP_EMMC || STM32MP_SPI_NOR) && PSA_FWU_SUPPORT */ |
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#endif /* PSA_FWU_SUPPORT */ |
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