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feat(stm32mp2-fdts): introduce stm32mp25 SoCs family 

STM32MP25 family is composed of 4 SoCs defined as following:

-STM32MP251: common part composed of 1*Cortex-A35, common peripherals
like SDMMC, UART, SPI, I2C, PCIe, USB3, parallel and DSI display,
1*ETH ...

-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.

-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).

A second diversity layer exists for security features/ A35 frequency:
-STM32MP25xY, "Y" gives information:
 -Y = A means A35@1.2GHz + no cryp IP and no secure boot.
 -Y = C means A35@1.2GHz + cryp IP and secure boot.
 -Y = D means A35@1.5GHz + no cryp IP and no secure boot.
 -Y = F means A35@1.5GHz + cryp IP and secure boot.

Change-Id: Icd1351e20b862675d257dede55df190a90acbd59
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
pull/2003/head
Alexandre Torgue 4 years ago
committed by Yann Gautier
parent
87a940e027
commit
0dc283d29e
6 changed files with 329 additions and 0 deletions
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  1. 289
      fdts/stm32mp251.dtsi
  2. 6
      fdts/stm32mp253.dtsi
  3. 9
      fdts/stm32mp255.dtsi
  4. 9
      fdts/stm32mp257.dtsi
  5. 8
      fdts/stm32mp25xc.dtsi
  6. 8
      fdts/stm32mp25xf.dtsi

289
fdts/stm32mp251.dtsi
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@ -0,0 +1,289 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/clock/stm32mp25-clks.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stm32mp25-resets.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a35";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <48000000>;
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <64000000>;
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32000>;
};
clk_msi: clk-msi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <16000000>;
};
};
intc: interrupt-controller@4ac00000 {
compatible = "arm,cortex-a7-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0x0 0x4ac10000 0x0 0x1000>,
<0x0 0x4ac20000 0x0 0x2000>,
<0x0 0x4ac40000 0x0 0x2000>,
<0x0 0x4ac60000 0x0 0x2000>;
};
timer: timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges = <0x0 0x0 0x0 0x80000000>;
rifsc: rifsc@42080000 {
compatible = "st,stm32mp25-rifsc";
reg = <0x42080000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
usart2: serial@400e0000 {
compatible = "st,stm32h7-uart";
reg = <0x400e0000 0x400>;
clocks = <&rcc CK_KER_USART2>;
resets = <&rcc USART2_R>;
status = "disabled";
};
};
rcc: rcc@44200000 {
compatible = "st,stm32mp25-rcc";
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
pwr: pwr@44210000 {
compatible = "st,stm32mp25-pwr";
reg = <0x44210000 0x400>;
vddio1: vddio1 {
regulator-name = "vddio1";
};
vddio2: vddio2 {
regulator-name = "vddio2";
};
vddio3: vddio3 {
regulator-name = "vddio3";
};
vddio4: vddio4 {
regulator-name = "vddio4";
};
vddio: vddio {
regulator-name = "vddio";
};
};
syscfg: syscon@44230000 {
compatible = "st,stm32mp25-syscfg", "syscon";
reg = <0x44230000 0x10000>;
};
pinctrl: pinctrl@44240000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-pinctrl";
ranges = <0 0x44240000 0xa0400>;
pins-are-numbered;
gpioa: gpio@44240000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x0 0x400>;
clocks = <&rcc CK_BUS_GPIOA>;
st,bank-name = "GPIOA";
status = "disabled";
};
gpiob: gpio@44250000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x10000 0x400>;
clocks = <&rcc CK_BUS_GPIOB>;
st,bank-name = "GPIOB";
status = "disabled";
};
gpioc: gpio@44260000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x20000 0x400>;
clocks = <&rcc CK_BUS_GPIOC>;
st,bank-name = "GPIOC";
status = "disabled";
};
gpiod: gpio@44270000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x30000 0x400>;
clocks = <&rcc CK_BUS_GPIOD>;
st,bank-name = "GPIOD";
status = "disabled";
};
gpioe: gpio@44280000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x40000 0x400>;
clocks = <&rcc CK_BUS_GPIOE>;
st,bank-name = "GPIOE";
status = "disabled";
};
gpiof: gpio@44290000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x50000 0x400>;
clocks = <&rcc CK_BUS_GPIOF>;
st,bank-name = "GPIOF";
status = "disabled";
};
gpiog: gpio@442a0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x60000 0x400>;
clocks = <&rcc CK_BUS_GPIOG>;
st,bank-name = "GPIOG";
status = "disabled";
};
gpioh: gpio@442b0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x70000 0x400>;
clocks = <&rcc CK_BUS_GPIOH>;
st,bank-name = "GPIOH";
status = "disabled";
};
gpioi: gpio@442c0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x80000 0x400>;
clocks = <&rcc CK_BUS_GPIOI>;
st,bank-name = "GPIOI";
status = "disabled";
};
gpioj: gpio@442d0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0x90000 0x400>;
clocks = <&rcc CK_BUS_GPIOJ>;
st,bank-name = "GPIOJ";
status = "disabled";
};
gpiok: gpio@442e0000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0xa0000 0x400>;
clocks = <&rcc CK_BUS_GPIOK>;
st,bank-name = "GPIOK";
status = "disabled";
};
};
pinctrl_z: pinctrl@46200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32mp257-z-pinctrl";
ranges = <0 0x46200000 0x400>;
pins-are-numbered;
gpioz: gpio@46200000 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
reg = <0 0x400>;
clocks = <&rcc CK_BUS_GPIOZ>;
st,bank-name = "GPIOZ";
st,bank-ioport = <11>;
status = "disabled";
};
};
};
};

6
fdts/stm32mp253.dtsi
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp251.dtsi"

9
fdts/stm32mp255.dtsi
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp253.dtsi"
/ {
};

9
fdts/stm32mp257.dtsi
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp255.dtsi"
/ {
};

8
fdts/stm32mp25xc.dtsi
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@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};

8
fdts/stm32mp25xf.dtsi
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@ -0,0 +1,8 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* Copyright (C) 2023, STMicroelectronics - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
/ {
};
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