Merge "feat(st): update the security based on new compatible" into integration

drivers/st/clk/stm32mp1_clk.c

@@ -1837,11 +1837,6 @@ int stm32mp1_clk_init(void)
 		return -FDT_ERR_NOTFOUND;
 	}
 
-	/* Check status field to disable security */
-	if (!fdt_get_rcc_secure_status()) {
-		mmio_write_32(rcc_base + RCC_TZCR, 0);
-	}
-
 	ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB,
 					clksrc);
 	if (ret < 0) {
@@ -2358,6 +2353,12 @@ static const struct clk_ops stm32mp_clk_ops = {
 
 int stm32mp1_clk_probe(void)
 {
+#if defined(IMAGE_BL32)
+	if (!fdt_get_rcc_secure_state()) {
+		mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U);
+	}
+#endif
+
 	stm32mp1_osc_init();
 
 	sync_earlyboot_clocks_state();

drivers/st/clk/stm32mp_clkfunc.c

@@ -250,24 +250,22 @@ const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
 }
 
 /*
- * Get the secure status for rcc node in device tree.
- * @return: true if rcc is available from secure world, false if not.
+ * Get the secure state for rcc node in device tree.
+ * @return: true if rcc is configured for secure world access, false if not.
  */
-bool fdt_get_rcc_secure_status(void)
+bool fdt_get_rcc_secure_state(void)
 {
-	int node;
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
 		return false;
 	}
 
-	node = fdt_get_rcc_node(fdt);
-	if (node < 0) {
+	if (fdt_node_offset_by_compatible(fdt, -1, DT_RCC_SEC_CLK_COMPAT) < 0) {
 		return false;
 	}
 
-	return !!(fdt_get_status(node) & DT_SECURE);
+	return true;
 }
 
 /*

include/drivers/st/stm32mp_clkfunc.h

@@ -23,7 +23,7 @@ int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
 			      uint32_t *array);
 int fdt_rcc_subnode_offset(const char *name);
 const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
-bool fdt_get_rcc_secure_status(void);
+bool fdt_get_rcc_secure_state(void);
 
 int fdt_get_clock_id(int node);
 unsigned long fdt_get_uart_clock_freq(uintptr_t instance);

plat/st/stm32mp1/stm32mp1_def.h

@@ -492,5 +492,6 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
 #define DT_NVMEM_LAYOUT_COMPAT		"st,stm32-nvmem-layout"
 #define DT_PWR_COMPAT			"st,stm32mp1,pwr-reg"
 #define DT_RCC_CLK_COMPAT		"st,stm32mp1-rcc"
+#define DT_RCC_SEC_CLK_COMPAT		"st,stm32mp1-rcc-secure"
 
 #endif /* STM32MP1_DEF_H */