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@ -1,5 +1,5 @@ |
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/* |
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
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* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved. |
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* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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@ -207,7 +207,14 @@ func denver_disable_dco |
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2: ret |
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endfunc denver_disable_dco |
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func check_errata_cve_2017_5715 |
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workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
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#if IMAGE_BL31 |
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adr x1, workaround_bpflush_runtime_exceptions |
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msr vbar_el3, x1 |
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#endif |
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workaround_reset_end denver, CVE(2017, 5715) |
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check_erratum_custom_start denver, CVE(2017, 5715) |
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mov x0, #ERRATA_MISSING |
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#if WORKAROUND_CVE_2017_5715 |
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/* |
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@ -224,43 +231,9 @@ func check_errata_cve_2017_5715 |
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1: |
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#endif |
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ret |
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endfunc check_errata_cve_2017_5715 |
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func check_errata_cve_2018_3639 |
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#if WORKAROUND_CVE_2018_3639 |
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mov x0, #ERRATA_APPLIES |
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#else |
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mov x0, #ERRATA_MISSING |
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#endif |
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ret |
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endfunc check_errata_cve_2018_3639 |
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/* ------------------------------------------------- |
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* The CPU Ops reset function for Denver. |
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* ------------------------------------------------- |
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*/ |
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func denver_reset_func |
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mov x19, x30 |
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 |
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/* |
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* Check if the CPU supports the special instruction |
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* required to flush the indirect branch predictor and |
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* RSB. Support for this operation can be determined by |
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* comparing bits 19:16 of ID_AFR0_EL1 with 0b0001. |
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*/ |
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mrs x0, id_afr0_el1 |
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mov x1, #0x10000 |
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and x0, x0, x1 |
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cmp x0, #0 |
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adr x1, workaround_bpflush_runtime_exceptions |
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mrs x2, vbar_el3 |
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csel x0, x1, x2, ne |
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msr vbar_el3, x0 |
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#endif |
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check_erratum_custom_end denver, CVE(2017, 5715) |
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#if WORKAROUND_CVE_2018_3639 |
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workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
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/* |
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* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different |
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* bits in the ACTLR_EL3 register to disable speculative |
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@ -277,8 +250,11 @@ func denver_reset_func |
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msr actlr_el3, x0 |
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isb |
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dsb sy |
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#endif |
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workaround_reset_end denver, CVE(2018, 3639) |
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check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
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cpu_reset_func_start denver |
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/* ---------------------------------------------------- |
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* Reset ACTLR.PMSTATE to C1 state |
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* ---------------------------------------------------- |
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@ -293,9 +269,7 @@ func denver_reset_func |
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* ---------------------------------------------------- |
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*/ |
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bl denver_enable_dco |
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ret x19 |
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endfunc denver_reset_func |
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cpu_reset_func_end denver |
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/* ---------------------------------------------------- |
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* The CPU Ops core power down function for Denver. |
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@ -322,27 +296,7 @@ func denver_cluster_pwr_dwn |
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ret |
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endfunc denver_cluster_pwr_dwn |
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#if REPORT_ERRATA |
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/* |
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* Errata printing function for Denver. Must follow AAPCS. |
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*/ |
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func denver_errata_report |
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stp x8, x30, [sp, #-16]! |
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bl cpu_get_rev_var |
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mov x8, x0 |
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/* |
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* Report all errata. The revision-variant information is passed to |
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* checking functions of each errata. |
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*/ |
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report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715 |
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report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639 |
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ldp x8, x30, [sp], #16 |
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ret |
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endfunc denver_errata_report |
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#endif |
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errata_report_shim denver |
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/* --------------------------------------------- |
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* This function provides Denver specific |
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@ -367,7 +321,7 @@ endfunc denver_cpu_reg_dump |
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.macro denver_cpu_ops_wa midr |
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declare_cpu_ops_wa denver, \midr, \ |
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denver_reset_func, \ |
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check_errata_cve_2017_5715, \ |
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check_erratum_denver_5715, \ |
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CPU_NO_EXTRA2_FUNC, \ |
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CPU_NO_EXTRA3_FUNC, \ |
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denver_core_pwr_dwn, \ |
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