errata: workaround for Neoverse V1 errata 1966096

Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1
processor core.  This issue is present in revisions r0p0, r1p0,
and r1p1, but the workaround only applies to r1p0 and r1p1, it is still
open.

SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b

docs/design/cpu-specific-build-macros.rst

@@ -344,6 +344,11 @@ For Neoverse V1, the following errata build flags are defined :
    CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
    CPU.
 
+-  ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
+   CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
+   issue is present in r0p0 as well but there is no workaround for that
+   revision.  It is still open.
+
 DSU Errata Workarounds
 ----------------------
 

lib/cpus/aarch64/neoverse_v1.S

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -188,6 +188,42 @@ func check_errata_1940577
 	b	cpu_rev_var_range
 endfunc check_errata_1940577
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Neoverse V1 Errata #1966096
+	 * This applies to revisions r1p0 - r1p1 and is open.
+	 * It also exists in r0p0 but there is no workaround
+	 * for that revision.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_neoverse_v1_1966096_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_1966096
+	cbz	x0, 1f
+
+	/* Apply the workaround. */
+	mov	x0, #0x3
+	msr	S3_6_C15_C8_0, x0
+	ldr	x0, =0xEE010F12
+	msr	S3_6_C15_C8_2, x0
+	ldr	x0, =0xFFFF0FFF
+	msr	S3_6_C15_C8_3, x0
+	ldr	x0, =0x80000000003FF
+	msr	S3_6_C15_C8_1, x0
+	isb
+
+1:
+	ret	x17
+endfunc errata_neoverse_v1_1966096_wa
+
+func check_errata_1966096
+	mov	x1, #0x10
+	mov	x2, #0x11
+	b	cpu_rev_var_range
+endfunc check_errata_1966096
+
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -223,6 +259,7 @@ func neoverse_v1_errata_report
 	report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
 	report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
 	report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
+	report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -261,6 +298,11 @@ func neoverse_v1_reset_func
 	bl	errata_neoverse_v1_1940577_wa
 #endif
 
+#if ERRATA_V1_1966096
+	mov	x0, x18
+	bl	errata_neoverse_v1_1966096_wa
+#endif
+
 	ret	x19
 endfunc neoverse_v1_reset_func
 

lib/cpus/cpu-ops.mk

@@ -392,6 +392,11 @@ ERRATA_V1_1925756	?=0
 # to revisions r1p0 and r1p1 of the Neoverse V1 cpu.
 ERRATA_V1_1940577	?=0
 
+# Flag to apply erratum 1966096 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open.  This issue
+# exists in r0p0 as well but there is no workaround for that revision.
+ERRATA_V1_1966096   ?=0
+
 # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
 # Applying the workaround results in higher DSU power consumption on idle.
 ERRATA_DSU_798953	?=0
@@ -717,6 +722,10 @@ $(eval $(call add_define,ERRATA_V1_1925756))
 $(eval $(call assert_boolean,ERRATA_V1_1940577))
 $(eval $(call add_define,ERRATA_V1_1940577))
 
+# Process ERRATA_V1_1966096 flag
+$(eval $(call assert_boolean,ERRATA_V1_1966096))
+$(eval $(call add_define,ERRATA_V1_1966096))
+
 # Process ERRATA_DSU_798953 flag
 $(eval $(call assert_boolean,ERRATA_DSU_798953))
 $(eval $(call add_define,ERRATA_DSU_798953))