feat(nxp/driver/dcfg): add some macro definition

Added offset for register DEVDISR2 and DEVDISR3, added
bit definiton for PORSR1_RCW, and some macro for SVR.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: Ie49392b89280c6c2c3510fcb4c85d827a1efdac0

include/drivers/nxp/dcfg/dcfg_lsch2.h

@@ -11,6 +11,8 @@
 /* dcfg block register offsets and bitfields */
 #define DCFG_PORSR1_OFFSET		0x00
 #define DCFG_DEVDISR1_OFFSET		0x070
+#define DCFG_DEVDISR2_OFFSET		0x074
+#define DCFG_DEVDISR3_OFFSET		0x078
 #define DCFG_DEVDISR4_OFFSET		0x07C
 #define DCFG_DEVDISR5_OFFSET		0x080
 #define DCFG_COREDISR_OFFSET		0x094
@@ -29,6 +31,10 @@
 #define DCFG_RSTRQSR1_OFFSET		0x0C8
 #define DCFG_RSTRQMR1_OFFSET		0x0C0
 
+/* PORSR1 bit mask */
+#define PORSR1_RCW_MASK			0xff800000
+#define PORSR1_RCW_SHIFT		23
+
 /* DCFG DCSR Macros */
 #define DCFG_DCSR_PORCR1_OFFSET		0x0
 
@@ -43,6 +49,8 @@
 #define SVR_MAJ_VER_MASK		0xF0
 #define SVR_MAJ_VER_SHIFT		4
 #define SVR_MIN_VER_MASK		0xF
+#define SVR_MINOR_VER_0			0x00
+#define SVR_MINOR_VER_1			0x01
 
 #define DISR5_DDRC1_MASK		0x1
 #define DISR5_OCRAM_MASK		0x40