feat(tc): factor in FVP/FPGA differences

Even though the FVP and FPGA are meant to be identical their RoS's (rest
of system) are different. Factor these in so the device tree works for
both. The differences are:
 * addresses of GIC and UART
 * displays (FPGA uses 4k)
 * ethernet devices and SD card (it's non removable on the FPGA)

Their frequencies are also different. The FVP simulates certain
frequencies but isn't very sensitive when we disregard them. To keep
code similar, update them with the FPGA values. This keeps working on
FVP even if slightly incorrect.

Also add an option for the DPU to either use fixed clocks or SCMI set
clocks, hidden behind a flag. This is useful during bringup and because
SCMI may not necessarily work on FPGA.

Co-developed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Co-developed-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Co-developed-by: Usama Arif <usama.arif@arm.com>
Co-developed-by: Angel Rodriguez Garcia <angel.rodriguezgarcia@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: Ic7a4bfc302673a3a6571757e23a9e6184fba2a13

fdts/tc.dts

@@ -22,7 +22,7 @@
 	};
 
 	chosen {
-		stdout-path = "serial0:115200n8";
+		stdout-path = STDOUT_PATH;
 	};
 
 	cpus {
@@ -411,7 +411,7 @@
 		};
 	};
 
-	gic: interrupt-controller@2c010000 {
+	gic: interrupt-controller@GIC_CTRL_ADDR {
 		compatible = "arm,gic-v3";
 		#address-cells = <2>;
 		#interrupt-cells = <3>;
@@ -419,7 +419,7 @@
 		ranges;
 		interrupt-controller;
 		reg = <0x0 0x30000000 0 0x10000>, /* GICD */
-		      <0x0 0x30080000 0 0x200000>; /* GICR */
+		      <0x0 0x30080000 0 GIC_GICR_OFFSET>; /* GICR */
 		interrupts = <GIC_PPI 0x9 IRQ_TYPE_LEVEL_LOW>;
 	};
 
@@ -434,7 +434,7 @@
 	soc_refclk: refclk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
-		clock-frequency = <100000000>;
+		clock-frequency = <1000000000>;
 		clock-output-names = "apb_pclk";
 	};
 
@@ -452,9 +452,10 @@
 		clock-output-names = "uartclk";
 	};
 
+	/* soc_uart0 on FPGA, ap_ns_uart on FVP */
 	os_uart: serial@2a400000 {
 		compatible = "arm,pl011", "arm,primecell";
-		reg = <0x0 0x2A400000 0x0 0x1000>;
+		reg = <0x0 0x2A400000 0x0 UART_OFFSET>;
 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&soc_uartclk>, <&soc_refclk>;
 		clock-names = "uartclk", "apb_pclk";
@@ -479,24 +480,21 @@
 
 		display-timings {
 			timing-panel {
-				clock-frequency = <25175000>;
+				VENCODER_TIMING;
-				hactive = <640>;
-				vactive = <480>;
-				hfront-porch = <16>;
-				hback-porch = <48>;
-				hsync-len = <96>;
-				vfront-porch = <10>;
-				vback-porch = <33>;
-				vsync-len = <2>;
 			};
 		};
 
 	};
 
 	ethernet@18000000 {
-		compatible = "smsc,lan91c111";
+		compatible = ETH_COMPATIBLE;
 		reg = <0x0 0x18000000 0x0 0x10000>;
 		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+
+		/* FPGA only but will work on FVP. Keep for simplicity */
+		phy-mode = "mii";
+		reg-io-width = <2>;
+		smsc,irq-push-pull;
 	};
 
 	kmi@1c060000 {
@@ -549,10 +547,10 @@
 		reg = <0x0 0x001c050000 0x0 0x1000>;
 		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
 			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
-		cd-gpios = <&sysreg 0 0>;
+		MMC_REMOVABLE;
 		wp-gpios = <&sysreg 1 0>;
-		bus-width = <8>;
+		bus-width = <4>;
-		max-frequency = <12000000>;
+		max-frequency = <25000000>;
 		vmmc-supply = <&fixed_3v3>;
 		clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
 		clock-names = "mclk", "apb_pclk";
@@ -614,14 +612,12 @@
 		reg = <0 0x2cc00000 0 0x20000>;
 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 		interrupt-names = "DPU";
-		clocks = <&scmi_clk 0>;
+		DPU_CLK_ATTR1;
-		clock-names = "aclk";
 		iommus = <&smmu_700 0x100>;
 		power-domains = <&scmi_devpd DPU_SCMI_PD_IDX>;
 		pl0: pipeline@0 {
 			reg = <0>;
-			clocks = <&scmi_clk 1>;
+			DPU_CLK_ATTR2;
-			clock-names = "pxclk";
 			pl_id = <0>;
 			ports {
 				#address-cells = <1>;
@@ -637,8 +633,7 @@
 
 		pl1: pipeline@1 {
 			reg = <1>;
-			clocks = <&scmi_clk 2>;
+			DPU_CLK_ATTR3;
-			clock-names = "pxclk";
 			pl_id = <1>;
 			ports {
 				#address-cells = <1>;

fdts/tc_vers.dtsi

@@ -41,6 +41,73 @@
 #define UARTCLK_FREQ		3750000
 #endif /* TARGET_PLATFORM == 3 */
 
+#if TARGET_FLAVOUR_FVP
+#define STDOUT_PATH		"serial0:115200n8"
+#define GIC_CTRL_ADDR		2c010000
+#define GIC_GICR_OFFSET		0x200000
+#define UART_OFFSET		0x1000
+#define VENCODER_TIMING_CLK 25175000
+#define VENCODER_TIMING								\
+	clock-frequency = <VENCODER_TIMING_CLK>;				\
+	hactive = <640>;							\
+	vactive = <480>;							\
+	hfront-porch = <16>;							\
+	hback-porch = <48>;							\
+	hsync-len = <96>;							\
+	vfront-porch = <10>;							\
+	vback-porch = <33>;							\
+	vsync-len = <2>
+#define ETH_COMPATIBLE		"smsc,lan91c111"
+#define MMC_REMOVABLE		cd-gpios = <&sysreg 0 0>
+
+#else /* TARGET_FLAVOUR_FPGA */
+
+#define STDOUT_PATH		"serial0:38400n8"
+#define GIC_CTRL_ADDR		30000000
+#define GIC_GICR_OFFSET		0x1000000
+#define UART_OFFSET		0x10000
+/* 1440x3200@120 framebuffer */
+#define VENCODER_TIMING_CLK 836000000
+#define VENCODER_TIMING								\
+	clock-frequency = <VENCODER_TIMING_CLK>;				\
+	hactive = <1440>;							\
+	vactive = <3200>;							\
+	hfront-porch = <136>;							\
+	hback-porch = <296>;							\
+	hsync-len = <160>;							\
+	vfront-porch = <3>;							\
+	vback-porch = <217>;							\
+	vsync-len = <10>
+#define ETH_COMPATIBLE		"smsc,lan9115"
+#define MMC_REMOVABLE		non-removable
+#endif /* TARGET_FLAVOUR_FPGA */
+
+/* Use SCMI controlled clocks */
+#if TC_DPU_USE_SCMI_CLK
+#define DPU_CLK_ATTR1								\
+	clocks = <&scmi_clk 0>;							\
+	clock-names = "aclk"
+
+#define DPU_CLK_ATTR2								\
+	clocks = <&scmi_clk 1>;							\
+	clock-names = "pxclk"
+
+#define DPU_CLK_ATTR3								\
+	clocks = <&scmi_clk 2>;							\
+	clock-names = "pxclk"							\
+/* Use fixed clocks */
+#else /* !TC_DPU_USE_SCMI_CLK */
+#define DPU_CLK_ATTR1								\
+	clocks = <&dpu_aclk>;							\
+	clock-names = "aclk"
+
+#define DPU_CLK_ATTR2								\
+	clocks = <&dpu_pixel_clk>, <&dpu_aclk>;					\
+	clock-names = "pxclk", "aclk"
+
+#define DPU_CLK_ATTR3 DPU_CLK_ATTR2
+#endif /* !TC_DPU_USE_SCMI_CLK */
+
 / {
 #if TARGET_PLATFORM <= 2
 	cmn-pmu {
@@ -49,4 +116,20 @@
 		interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
 	};
 #endif /* TARGET_PLATFORM <= 2 */
+
+#if !TC_DPU_USE_SCMI_CLK
+	dpu_aclk: dpu_aclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <VENCODER_TIMING_CLK>;
+		clock-output-names = "fpga:dpu_aclk";
+	};
+
+	dpu_pixel_clk: dpu-pixel-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <VENCODER_TIMING_CLK>;
+		clock-output-names = "pxclk";
+	};
+#endif /* !TC_DPU_USE_SCMI_CLK */
 };

plat/arm/board/tc/include/platform_def.h

@@ -184,6 +184,13 @@
 #define TC_DEVICE_BASE			0x21000000
 #define TC_DEVICE_SIZE			0x5f000000
 
+#if defined(TARGET_FLAVOUR_FPGA)
+#undef V2M_FLASH0_BASE
+#undef V2M_FLASH0_SIZE
+#define V2M_FLASH0_BASE			UL(0x0C000000)
+#define V2M_FLASH0_SIZE			UL(0x02000000)
+#endif
+
 // TC_MAP_DEVICE covers different peripherals
 // available to the platform
 #define TC_MAP_DEVICE	MAP_REGION_FLAT(		\
@@ -204,7 +211,11 @@
 #define PLAT_ARM_TRUSTED_ROM_SIZE	(0x00080000 - PLAT_ARM_TRUSTED_ROM_BASE)
 
 #define PLAT_ARM_NSRAM_BASE		0x06000000
+#if TARGET_FLAVOUR_FVP
 #define PLAT_ARM_NSRAM_SIZE		0x00080000	/* 512KB */
+#else /* TARGET_FLAVOUR_FPGA */
+#define PLAT_ARM_NSRAM_SIZE		0x00008000	/* 64KB */
+#endif /* TARGET_FLAVOUR_FPGA */
 
 #if TARGET_PLATFORM <= 2
 #define PLAT_ARM_DRAM2_BASE		ULL(0x8080000000)
@@ -349,16 +360,41 @@
 
 /* UART related constants */
 
-#undef PLAT_ARM_BOOT_UART_BASE
+#define TC_UART0			0x2a400000
-#define PLAT_ARM_BOOT_UART_BASE		0x2A410000
+#define TC_UART1			0x2a410000
 
+/*
+ * TODO: if any more undefs are needed, it's better to consider dropping the
+ * board_css_def.h include above
+ */
+#undef PLAT_ARM_BOOT_UART_BASE
 #undef PLAT_ARM_RUN_UART_BASE
-#define PLAT_ARM_RUN_UART_BASE		0x2A400000
-
 #undef PLAT_ARM_SP_MIN_RUN_UART_BASE
 #define PLAT_ARM_SP_MIN_RUN_UART_BASE	PLAT_ARM_RUN_UART_BASE
 
 #undef PLAT_ARM_CRASH_UART_BASE
+#undef PLAT_ARM_BOOT_UART_CLK_IN_HZ
+#undef PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+#if TARGET_FLAVOUR_FVP
+#define PLAT_ARM_BOOT_UART_BASE		TC_UART1
+#define TC_UARTCLK			7372800
+#else /* TARGET_FLAVOUR_FPGA */
+#define PLAT_ARM_BOOT_UART_BASE		TC_UART0
+#if TARGET_PLATFORM <= 2
+#define TC_UARTCLK			5000000
+#elif TARGET_PLATFORM >= 3
+#define TC_UARTCLK			3750000
+#endif /* TARGET_PLATFORM >= 3 */
+#undef  ARM_CONSOLE_BAUDRATE
+#define ARM_CONSOLE_BAUDRATE		38400
+#endif /* TARGET_FLAVOUR_FPGA */
+
+#define PLAT_ARM_RUN_UART_BASE		TC_UART0
+#define PLAT_ARM_SP_MIN_RUN_UART_BASE	PLAT_ARM_RUN_UART_BASE
 #define PLAT_ARM_CRASH_UART_BASE	PLAT_ARM_RUN_UART_BASE
 
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ	TC_UARTCLK
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ	TC_UARTCLK
+
 #endif /* PLATFORM_DEF_H */

plat/arm/board/tc/platform.mk

@@ -6,6 +6,8 @@
 include common/fdt_wrappers.mk
 
 TARGET_FLAVOUR			:=	fvp
+# DPU with SCMI may not necessarily work, so allow its independence
+TC_DPU_USE_SCMI_CLK		:=	1
 
 ifneq ($(shell expr $(TARGET_PLATFORM) \<= 1), 0)
         $(warning Platform ${PLAT}$(TARGET_PLATFORM) is deprecated. \
@@ -23,6 +25,7 @@ endif
 $(eval $(call add_defines, \
 	TARGET_PLATFORM \
 	TARGET_FLAVOUR_$(call uppercase,${TARGET_FLAVOUR}) \
+	TC_DPU_USE_SCMI_CLK \
 ))
 
 CSS_LOAD_SCP_IMAGES	:=	1