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In contrast with the non-multi-threading DTS, this enumerates MPIDR values shifted by one affinity level to the left. The newly added DTS reflects CPUs with a single thread in them. Since both DTS files are the same apart from MPIDR contents, the common bits have been moved to a separate file that's then included from the top-level DTS files. The multi-threading version only updates the MPIDR contents. Change-Id: Id225cd93574f764171df8962ac76f42fcb6bba4b Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>pull/1046/head
Jeenu Viswambharan
7 years ago
4 changed files with 310 additions and 262 deletions
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/* |
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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/dts-v1/; |
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/include/ "fvp-base-gicv3-psci-common.dtsi" |
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&CPU0 { |
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reg = <0x0 0x0>; |
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}; |
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&CPU1 { |
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reg = <0x0 0x100>; |
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}; |
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&CPU2 { |
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reg = <0x0 0x200>; |
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}; |
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&CPU3 { |
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reg = <0x0 0x300>; |
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}; |
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&CPU4 { |
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reg = <0x0 0x10000>; |
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}; |
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&CPU5 { |
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reg = <0x0 0x10100>; |
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}; |
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&CPU6 { |
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reg = <0x0 0x10200>; |
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}; |
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&CPU7 { |
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reg = <0x0 0x10300>; |
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}; |
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/* |
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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/memreserve/ 0x80000000 0x00010000; |
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/ { |
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}; |
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/ { |
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model = "FVP Base"; |
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compatible = "arm,vfp-base", "arm,vexpress"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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chosen { }; |
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aliases { |
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serial0 = &v2m_serial0; |
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serial1 = &v2m_serial1; |
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serial2 = &v2m_serial2; |
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serial3 = &v2m_serial3; |
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}; |
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psci { |
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; |
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method = "smc"; |
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cpu_suspend = <0xc4000001>; |
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cpu_off = <0x84000002>; |
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cpu_on = <0xc4000003>; |
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sys_poweroff = <0x84000008>; |
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sys_reset = <0x84000009>; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&CPU0>; |
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}; |
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core1 { |
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cpu = <&CPU1>; |
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}; |
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core2 { |
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cpu = <&CPU2>; |
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}; |
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core3 { |
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cpu = <&CPU3>; |
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}; |
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}; |
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cluster1 { |
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core0 { |
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cpu = <&CPU4>; |
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}; |
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core1 { |
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cpu = <&CPU5>; |
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}; |
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core2 { |
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cpu = <&CPU6>; |
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}; |
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core3 { |
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cpu = <&CPU7>; |
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}; |
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}; |
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}; |
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idle-states { |
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entry-method = "arm,psci"; |
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CPU_SLEEP_0: cpu-sleep-0 { |
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compatible = "arm,idle-state"; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x0010000>; |
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entry-latency-us = <40>; |
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exit-latency-us = <100>; |
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min-residency-us = <150>; |
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}; |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "arm,idle-state"; |
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local-timer-stop; |
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arm,psci-suspend-param = <0x1010000>; |
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entry-latency-us = <500>; |
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exit-latency-us = <1000>; |
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min-residency-us = <2500>; |
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}; |
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}; |
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CPU0:cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU1:cpu@1 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x1>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU2:cpu@2 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x2>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU3:cpu@3 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x3>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU4:cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU5:cpu@101 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x101>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU6:cpu@102 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x102>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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CPU7:cpu@103 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x103>; |
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enable-method = "psci"; |
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
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next-level-cache = <&L2_0>; |
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}; |
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L2_0: l2-cache0 { |
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compatible = "cache"; |
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}; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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reg = <0x00000000 0x80000000 0 0x7F000000>, |
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<0x00000008 0x80000000 0 0x80000000>; |
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}; |
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gic: interrupt-controller@2f000000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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interrupt-controller; |
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reg = <0x0 0x2f000000 0 0x10000>, // GICD |
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<0x0 0x2f100000 0 0x200000>, // GICR |
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<0x0 0x2c000000 0 0x2000>, // GICC |
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<0x0 0x2c010000 0 0x2000>, // GICH |
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<0x0 0x2c02f000 0 0x2000>; // GICV |
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interrupts = <1 9 4>; |
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its: its@2f020000 { |
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compatible = "arm,gic-v3-its"; |
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msi-controller; |
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reg = <0x0 0x2f020000 0x0 0x20000>; // GITS |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <1 13 0xff01>, |
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<1 14 0xff01>, |
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<1 11 0xff01>, |
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<1 10 0xff01>; |
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clock-frequency = <100000000>; |
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}; |
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timer@2a810000 { |
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compatible = "arm,armv7-timer-mem"; |
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reg = <0x0 0x2a810000 0x0 0x10000>; |
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clock-frequency = <100000000>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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frame@2a830000 { |
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frame-number = <1>; |
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interrupts = <0 26 4>; |
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reg = <0x0 0x2a830000 0x0 0x10000>; |
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}; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <0 60 4>, |
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<0 61 4>, |
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<0 62 4>, |
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<0 63 4>; |
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}; |
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smb { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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ranges = <0 0 0 0x08000000 0x04000000>, |
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<1 0 0 0x14000000 0x04000000>, |
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<2 0 0 0x18000000 0x04000000>, |
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<3 0 0 0x1c000000 0x04000000>, |
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<4 0 0 0x0c000000 0x04000000>, |
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<5 0 0 0x10000000 0x04000000>; |
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/include/ "rtsm_ve-motherboard.dtsi" |
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}; |
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panels { |
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panel@0 { |
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compatible = "panel"; |
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mode = "XVGA"; |
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refresh = <60>; |
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xres = <1024>; |
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yres = <768>; |
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pixclock = <15748>; |
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left_margin = <152>; |
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right_margin = <48>; |
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upper_margin = <23>; |
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lower_margin = <3>; |
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hsync_len = <104>; |
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vsync_len = <4>; |
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sync = <0>; |
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vmode = "FB_VMODE_NONINTERLACED"; |
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tim2 = "TIM2_BCD", "TIM2_IPC"; |
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cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)"; |
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caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888"; |
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bpp = <16>; |
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}; |
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}; |
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}; |
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