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build(intel): define a macro for SIMICS build

SIMICS builds have different UART configurations compared
to hardware build. Hence, this patch defines a macro to
differentiate between both.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iadecd5445e06611486ac3c6a214a6d0dc8ccd27b
pull/1985/head
Abdul Halim, Muhammad Hadi Asyrafi 4 years ago
committed by Sieu Mun Tang
parent
commit
1f1c0206d8
  1. 5
      Makefile
  2. 5
      plat/intel/soc/agilex/platform.mk
  3. 7
      plat/intel/soc/common/include/platform_def.h
  4. 1
      plat/intel/soc/n5x/platform.mk
  5. 5
      plat/intel/soc/stratix10/platform.mk

5
Makefile

@ -945,6 +945,9 @@ PRINT_MEMORY_MAP ?= ${PRINT_MEMORY_MAP_PATH}/print_memory_map.py
# Variables for use with documentation build using Sphinx tool
DOCS_PATH ?= docs
# Defination of SIMICS flag
SIMICS_BUILD ?= 0
################################################################################
# Include BL specific makefiles
################################################################################
@ -1055,6 +1058,7 @@ $(eval $(call assert_booleans,\
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
)))
$(eval $(call assert_numerics,\
@ -1172,6 +1176,7 @@ $(eval $(call add_defines,\
ENABLE_FEAT_FGT \
ENABLE_FEAT_AMUv1 \
ENABLE_FEAT_ECV \
SIMICS_BUILD \
)))
ifeq (${SANITIZE_UB},trap)

5
plat/intel/soc/agilex/platform.mk

@ -1,6 +1,6 @@
#
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -73,4 +73,5 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1

7
plat/intel/soc/common/include/platform_def.h

@ -169,9 +169,16 @@
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
#ifndef SIMICS_BUILD
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
#else
#define PLAT_BAUDRATE (4800)
#define PLAT_UART_CLOCK (76800)
#endif
/*******************************************************************************
* PHY related constants
******************************************************************************/

1
plat/intel/soc/n5x/platform.mk

@ -46,4 +46,5 @@ PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
BL2_INV_DCACHE := 0
MULTI_CONSOLE_API := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1

5
plat/intel/soc/stratix10/platform.mk

@ -1,6 +1,6 @@
#
# Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
# Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -69,4 +69,5 @@ BL31_SOURCES += \
PROGRAMMABLE_RESET_ADDRESS := 0
BL2_AT_EL3 := 1
SIMICS_BUILD := 0
USE_COHERENT_MEM := 1

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