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Merge changes from topic "jc/errata_refactor" into integration 

* changes:
  refactor(cpus): convert Cortex-A72 to use cpu helpers
  refactor(cpus): convert the Cortex-A72 to use the errata framework
  refactor(cpus): reorder Cortex-A72 errata by ascending order
pull/2000/head
Lauren Wehrmeister 1 year ago
committed by TrustedFirmware Code Review
parent
39f63170c7 64ea532dab
commit
231305ec0f
1 changed files with 60 additions and 131 deletions
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  1. 191
      lib/cpus/aarch64/cortex_a72.S

191
lib/cpus/aarch64/cortex_a72.S
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@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -47,9 +47,7 @@ endfunc cortex_a72_disable_l2_prefetch
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
mrs x0, CORTEX_A72_CPUACTLR_EL1
orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
msr CORTEX_A72_CPUACTLR_EL1, x0
sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
isb
dsb ish
ret
@ -60,9 +58,7 @@ endfunc cortex_a72_disable_hw_prefetcher
* ---------------------------------------------
*/
func cortex_a72_disable_smp
mrs x0, CORTEX_A72_ECTLR_EL1
bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
msr CORTEX_A72_ECTLR_EL1, x0
sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
ret
endfunc cortex_a72_disable_smp
@ -78,139 +74,95 @@ func cortex_a72_disable_ext_debug
ret
endfunc cortex_a72_disable_ext_debug
/* --------------------------------------------------
* Errata Workaround for Cortex A72 Errata #859971.
* This applies only to revision <= r0p3 of Cortex A72.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber:
* --------------------------------------------------
*/
func errata_a72_859971_wa
mov x17,x30
bl check_errata_859971
cbz x0, 1f
mrs x1, CORTEX_A72_CPUACTLR_EL1
orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
msr CORTEX_A72_CPUACTLR_EL1, x1
1:
ret x17
endfunc errata_a72_859971_wa
func check_errata_859971
mov x1, #0x03
b cpu_rev_var_ls
endfunc check_errata_859971
func check_errata_cve_2017_5715
func check_smccc_arch_workaround_3
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_errata_cve_2017_5715
endfunc check_smccc_arch_workaround_3
func check_errata_cve_2018_3639
#if WORKAROUND_CVE_2018_3639
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2018_3639
workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
workaround_reset_end cortex_a72, ERRATUM(859971)
/* --------------------------------------------------
* Errata workaround for Cortex A72 Errata #1319367.
* This applies to all revisions of Cortex A72.
* --------------------------------------------------
*/
func check_errata_1319367
#if ERRATA_A72_1319367
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
/* Due to the nature of the errata it is applied unconditionally when chosen */
check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
/* erratum workaround is interleaved with generic code */
add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET
workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
#if IMAGE_BL31
override_vector_table wa_cve_2017_5715_mmu_vbar
#endif
ret
endfunc check_errata_1319367
workaround_reset_end cortex_a72, CVE(2017, 5715)
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
check_erratum_custom_start cortex_a72, CVE(2017, 5715)
cpu_check_csv2 x0, 1f
#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
endfunc check_errata_cve_2022_23960
func check_smccc_arch_workaround_3
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
endfunc check_smccc_arch_workaround_3
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A72.
* -------------------------------------------------
*/
func cortex_a72_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A72_859971
mov x0, x18
bl errata_a72_859971_wa
#endif
check_erratum_custom_end cortex_a72, CVE(2017, 5715)
#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_mmu_vbar
msr vbar_el3, x0
/* isb will be performed before returning from this function */
workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
isb
dsb sy
workaround_reset_end cortex_a72, CVE(2018, 3639)
check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
/* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */
b 2f
1:
#if WORKAROUND_CVE_2022_23960
workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/* Skip installing vector table again if already done for CVE(2017, 5715) */
/*
* The Cortex-A72 generic vectors are overridden to apply the
* mitigation on exception entry from lower ELs for revisions >= r1p0
* mitigation on exception entry from lower ELs for revisions >= r1p0
* which has CSV2 implemented.
*/
adr x0, wa_cve_vbar_cortex_a72
mrs x1, vbar_el3
cmp x0, x1
b.eq 1f
msr vbar_el3, x0
1:
#endif /* IMAGE_BL31 */
workaround_reset_end cortex_a72, CVE(2022, 23960)
/* isb will be performed before returning from this function */
check_erratum_custom_start cortex_a72, CVE(2022, 23960)
#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
cpu_check_csv2 x0, 1f
mov x0, #ERRATA_APPLIES
ret
1:
#if WORKAROUND_CVE_2022_23960
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif /* WORKAROUND_CVE_2022_23960 */
2:
#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
ret
#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
mov x0, #ERRATA_MISSING
ret
check_erratum_custom_end cortex_a72, CVE(2022, 23960)
#if WORKAROUND_CVE_2018_3639
mrs x0, CORTEX_A72_CPUACTLR_EL1
orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
msr CORTEX_A72_CPUACTLR_EL1, x0
isb
dsb sy
#endif
cpu_reset_func_start cortex_a72
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
mrs x0, CORTEX_A72_ECTLR_EL1
orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
msr CORTEX_A72_ECTLR_EL1, x0
isb
ret x19
endfunc cortex_a72_reset_func
sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
cpu_reset_func_end cortex_a72
/* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A72.
@ -319,30 +271,7 @@ func cortex_a72_cluster_pwr_dwn
b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
#if REPORT_ERRATA
/*
* Errata printing function for Cortex A72. Must follow AAPCS.
*/
func cortex_a72_errata_report
stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var
mov x8, x0
/*
* Report all errata. The revision-variant information is passed to
* checking functions of each errata.
*/
report_errata ERRATA_A72_859971, cortex_a72, 859971
report_errata ERRATA_A72_1319367, cortex_a72, 1319367
report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960
ldp x8, x30, [sp], #16
ret
endfunc cortex_a72_errata_report
#endif
errata_report_shim cortex_a72
/* ---------------------------------------------
* This function provides cortex_a72 specific
@ -367,7 +296,7 @@ endfunc cortex_a72_cpu_reg_dump
declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
check_errata_cve_2017_5715, \
check_erratum_cortex_a72_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a72_core_pwr_dwn, \

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