diff --git a/include/drivers/allwinner/axp.h b/include/drivers/allwinner/axp.h index 9c0035f96..222820b12 100644 --- a/include/drivers/allwinner/axp.h +++ b/include/drivers/allwinner/axp.h @@ -9,6 +9,10 @@ #include +#define AXP20X_MODE_REG 0x3e +#define AXP20X_MODE_I2C 0x00 +#define AXP20X_MODE_RSB 0x7c + #define NA 0xff enum { diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 0ca18adc3..841fea81d 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -125,11 +125,9 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) device_bit = BIT(6); break; case SUNXI_SOC_H6: - if (use_rsb) - return -ENODEV; - pin_func = 0x33; + pin_func = use_rsb ? 0x22 : 0x33; device_bit = BIT(16); - reset_offset = 0x19c; + reset_offset = use_rsb ? 0x1bc : 0x19c; break; case SUNXI_SOC_A64: pin_func = use_rsb ? 0x22 : 0x33; @@ -157,7 +155,7 @@ int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb) if (socid != SUNXI_SOC_H6) mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); else - mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x19c, device_bit | BIT(0)); + mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0)); /* assert, then de-assert reset of I2C/RSB controller */ mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 5b7d76ae9..80a69c340 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -92,21 +92,13 @@ static int rsb_init(void) if (ret) return ret; - /* Start with 400 KHz to issue the I2C->RSB switch command. */ - ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 400000); - if (ret) - return ret; - - /* - * Initiate an I2C transaction to write 0x7c into register 0x3e, - * switching the PMIC to RSB mode. - */ - ret = rsb_set_device_mode(0x7c3e00); + /* Switch to the recommended 3 MHz bus clock. */ + ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); if (ret) return ret; - /* Now in RSB mode, switch to the recommended 3 MHz. */ - ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); + /* Initiate an I2C transaction to switch the PMIC to RSB mode. */ + ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); if (ret) return ret; @@ -156,6 +148,11 @@ int sunxi_pmic_setup(uint16_t socid, const void *fdt) pmic = AXP803_RSB; axp_setup_regulators(fdt); + /* Switch the PMIC back to I2C mode. */ + ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C); + if (ret) + return ret; + break; default: return -ENODEV; diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h index 702db770f..1b716061b 100644 --- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h @@ -55,6 +55,7 @@ #define SUNXI_R_TWD_BASE 0x07020800 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_R_I2C_BASE 0x07081400 +#define SUNXI_R_RSB_BASE 0x07083000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_PIO_BASE 0x07022000 diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk index 4ecc57cf0..1c98919b1 100644 --- a/plat/allwinner/sun50i_h6/platform.mk +++ b/plat/allwinner/sun50i_h6/platform.mk @@ -8,4 +8,4 @@ include plat/allwinner/common/allwinner-common.mk BL31_SOURCES += drivers/allwinner/axp/axp805.c \ - drivers/mentor/i2c/mi2cv.c + drivers/allwinner/sunxi_rsb.c diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c index 443015bac..a7865a5d4 100644 --- a/plat/allwinner/sun50i_h6/sunxi_power.c +++ b/plat/allwinner/sun50i_h6/sunxi_power.c @@ -6,20 +6,17 @@ */ #include -#include -#include #include #include -#include -#include -#include +#include #include #include #include -#define AXP805_ADDR 0x36 +#define AXP805_HW_ADDR 0x745 +#define AXP805_RT_ADDR 0x3a static enum pmic_type { UNKNOWN, @@ -28,67 +25,67 @@ static enum pmic_type { int axp_read(uint8_t reg) { - uint8_t val; - int ret; - - ret = i2c_write(AXP805_ADDR, 0, 0, ®, 1); - if (ret == 0) - ret = i2c_read(AXP805_ADDR, 0, 0, &val, 1); - if (ret) { - ERROR("PMIC: Cannot read AXP805 register %02x\n", reg); - return ret; - } - - return val; + return rsb_read(AXP805_RT_ADDR, reg); } int axp_write(uint8_t reg, uint8_t val) { - int ret; - - ret = i2c_write(AXP805_ADDR, reg, 1, &val, 1); - if (ret) - ERROR("PMIC: Cannot write AXP805 register %02x\n", reg); - - return ret; + return rsb_write(AXP805_RT_ADDR, reg, val); } -static int axp805_probe(void) +static int rsb_init(void) { int ret; - /* Switch the AXP805 to master/single-PMIC mode. */ - ret = axp_write(0xff, 0x0); + ret = rsb_init_controller(); if (ret) return ret; - ret = axp_check_id(); + /* Switch to the recommended 3 MHz bus clock. */ + ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000); if (ret) return ret; - return 0; + /* Initiate an I2C transaction to switch the PMIC to RSB mode. */ + ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8); + if (ret) + return ret; + + /* Associate the 8-bit runtime address with the 12-bit bus address. */ + ret = rsb_assign_runtime_address(AXP805_HW_ADDR, AXP805_RT_ADDR); + if (ret) + return ret; + + return axp_check_id(); } int sunxi_pmic_setup(uint16_t socid, const void *fdt) { int ret; - INFO("PMIC: Probing AXP805 on I2C\n"); + INFO("PMIC: Probing AXP805 on RSB\n"); - ret = sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); + ret = sunxi_init_platform_r_twi(socid, true); if (ret) return ret; - /* initialise mi2cv driver */ - i2c_init((void *)SUNXI_R_I2C_BASE); + ret = rsb_init(); + if (ret) + return ret; - ret = axp805_probe(); + /* Switch the AXP805 to master/single-PMIC mode. */ + ret = axp_write(0xff, 0x0); if (ret) return ret; pmic = AXP805; axp_setup_regulators(fdt); + /* Switch the PMIC back to I2C mode. */ + ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C); + if (ret) + return ret; + return 0; } @@ -96,10 +93,9 @@ void sunxi_power_down(void) { switch (pmic) { case AXP805: - /* Re-initialise after rich OS might have used it. */ - sunxi_init_platform_r_twi(SUNXI_SOC_H6, false); - /* initialise mi2cv driver */ - i2c_init((void *)SUNXI_R_I2C_BASE); + /* (Re-)init RSB in case the rich OS has disabled it. */ + sunxi_init_platform_r_twi(SUNXI_SOC_H6, true); + rsb_init(); axp_power_off(); break; default: