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rockchip: set gpio2 ~ gpio4 to input and pull none mode 

For save power cosumption, if gpio power supply shut down, we need to
set gpio2 ~ gpio4 to input and HiZ status when suspend, and recovery
they status when rusume. we do it base on apio pass from loader.

Change-Id: I59fd2395e5e37e63425472a39f519822c9197e4c
pull/698/head
Caesar Wang 8 years ago
parent
e550c63101
commit
2bff35bb7c
5 changed files with 208 additions and 4 deletions
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  1. 14
      plat/rockchip/common/include/plat_params.h
  2. 1
      plat/rockchip/common/include/plat_private.h
  3. 12
      plat/rockchip/common/params_setup.c
  4. 158
      plat/rockchip/rk3399/drivers/pmu/pmu.c
  5. 27
      plat/rockchip/rk3399/drivers/pmu/pmu.h

14
plat/rockchip/common/include/plat_params.h
View File

@ -79,6 +79,15 @@ enum {
PARAM_RESET,
PARAM_POWEROFF,
PARAM_SUSPEND_GPIO,
PARAM_SUSPEND_APIO,
};
struct apio_info {
uint8_t apio1 : 1;
uint8_t apio2 : 1;
uint8_t apio3 : 1;
uint8_t apio4 : 1;
uint8_t apio5 : 1;
};
struct gpio_info {
@ -99,4 +108,9 @@ struct bl31_gpio_param {
struct gpio_info gpio;
};
struct bl31_apio_param {
struct bl31_plat_param h;
struct apio_info apio;
};
#endif /* __PLAT_PARAMS_H__ */

1
plat/rockchip/common/include/plat_private.h
View File

@ -124,6 +124,7 @@ void platform_cpu_warmboot(void);
struct gpio_info *plat_get_rockchip_gpio_reset(void);
struct gpio_info *plat_get_rockchip_gpio_poweroff(void);
struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count);
struct apio_info *plat_get_rockchip_suspend_apio(void);
void plat_rockchip_gpio_init(void);
extern const unsigned char rockchip_power_domain_tree_desc[];

12
plat/rockchip/common/params_setup.c
View File

@ -42,10 +42,12 @@
static struct gpio_info param_reset;
static struct gpio_info param_poweroff;
static struct bl31_apio_param param_apio;
static struct gpio_info *rst_gpio;
static struct gpio_info *poweroff_gpio;
static struct gpio_info suspend_gpio[10];
uint32_t suspend_gpio_cnt;
static struct apio_info *suspend_apio;
struct gpio_info *plat_get_rockchip_gpio_reset(void)
{
@ -64,6 +66,11 @@ struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count)
return &suspend_gpio[0];
}
struct apio_info *plat_get_rockchip_suspend_apio(void)
{
return suspend_apio;
}
void params_early_setup(void *plat_param_from_bl2)
{
struct bl31_plat_param *bl2_param;
@ -96,6 +103,11 @@ void params_early_setup(void *plat_param_from_bl2)
sizeof(struct gpio_info));
suspend_gpio_cnt++;
break;
case PARAM_SUSPEND_APIO:
memcpy(&param_apio, bl2_param,
sizeof(struct bl31_apio_param));
suspend_apio = &param_apio.apio;
break;
default:
ERROR("not expected type found %ld\n",
bl2_param->type);

158
plat/rockchip/rk3399/drivers/pmu/pmu.c
View File

@ -874,6 +874,159 @@ static void clr_hw_idle(uint32_t hw_idle)
mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
}
static uint32_t iomux_status[12];
static uint32_t pull_mode_status[12];
static uint32_t gpio_direction[3];
static uint32_t gpio_2_4_clk_gate;
static void suspend_apio(void)
{
struct apio_info *suspend_apio;
int i;
suspend_apio = plat_get_rockchip_suspend_apio();
if (!suspend_apio)
return;
/* save gpio2 ~ gpio4 iomux and pull mode */
for (i = 0; i < 12; i++) {
iomux_status[i] = mmio_read_32(GRF_BASE +
GRF_GPIO2A_IOMUX + i * 4);
pull_mode_status[i] = mmio_read_32(GRF_BASE +
GRF_GPIO2A_P + i * 4);
}
/* store gpio2 ~ gpio4 clock gate state */
gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >>
PCLK_GPIO2_GATE_SHIFT) & 0x07;
/* enable gpio2 ~ gpio4 clock gate */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
/* save gpio2 ~ gpio4 direction */
gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04);
gpio_direction[1] = mmio_read_32(GPIO3_BASE + 0x04);
gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04);
/* apio1 charge gpio3a0 ~ gpio3c7 */
if (suspend_apio->apio1) {
/* set gpio3a0 ~ gpio3c7 iomux to gpio */
mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
/* set gpio3a0 ~ gpio3c7 pull mode to pull none */
mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0);
/* set gpio3a0 ~ gpio3c7 to input */
mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff);
}
/* apio2 charge gpio2a0 ~ gpio2b4 */
if (suspend_apio->apio2) {
/* set gpio2a0 ~ gpio2b4 iomux to gpio */
mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
/* set gpio2a0 ~ gpio2b4 pull mode to pull none */
mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0);
/* set gpio2a0 ~ gpio2b4 to input */
mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff);
}
/* apio3 charge gpio2c0 ~ gpio2d4*/
if (suspend_apio->apio3) {
/* set gpio2a0 ~ gpio2b4 iomux to gpio */
mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
/* set gpio2c0 ~ gpio2d4 pull mode to pull none */
mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0);
/* set gpio2c0 ~ gpio2d4 to input */
mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000);
}
/* apio4 charge gpio4c0 ~ gpio4c7, gpio4d0 ~ gpio4d6 */
if (suspend_apio->apio4) {
/* set gpio4c0 ~ gpio4d6 iomux to gpio */
mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
/* set gpio4c0 ~ gpio4d6 pull mode to pull none */
mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0);
/* set gpio4c0 ~ gpio4d6 to input */
mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000);
}
/* apio5 charge gpio3d0 ~ gpio3d7, gpio4a0 ~ gpio4a7*/
if (suspend_apio->apio5) {
/* set gpio3d0 ~ gpio4a7 iomux to gpio */
mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX,
REG_SOC_WMSK | GRF_IOMUX_GPIO);
/* set gpio3d0 ~ gpio4a7 pull mode to pull none */
mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0);
mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0);
/* set gpio4c0 ~ gpio4d6 to input */
mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000);
mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff);
}
}
static void resume_apio(void)
{
struct apio_info *suspend_apio;
int i;
suspend_apio = plat_get_rockchip_suspend_apio();
if (!suspend_apio)
return;
for (i = 0; i < 12; i++) {
mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4,
REG_SOC_WMSK | pull_mode_status[i]);
mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
REG_SOC_WMSK | iomux_status[i]);
}
/* set gpio2 ~ gpio4 direction back to store value */
mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]);
mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]);
mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]);
/* set gpio2 ~ gpio4 clock gate back to store value */
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
BITS_WITH_WMASK(gpio_2_4_clk_gate, 0x07,
PCLK_GPIO2_GATE_SHIFT));
}
static void suspend_gpio(void)
{
struct gpio_info *suspend_gpio;
@ -950,7 +1103,6 @@ static int sys_pwr_domain_suspend(void)
}
}
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
/*
* Disabling PLLs/PWM/DVFS is approaching WFI which is
* the last steps in suspend.
@ -959,6 +1111,7 @@ static int sys_pwr_domain_suspend(void)
disable_dvfs_plls();
disable_pwms();
disable_nodvfs_plls();
suspend_apio();
suspend_gpio();
return 0;
@ -969,7 +1122,7 @@ static int sys_pwr_domain_resume(void)
uint32_t wait_cnt = 0;
uint32_t status = 0;
resume_apio();
resume_gpio();
enable_nodvfs_plls();
enable_pwms();
@ -986,7 +1139,6 @@ static int sys_pwr_domain_resume(void)
* somewhere.
*/
mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),

27
plat/rockchip/rk3399/drivers/pmu/pmu.h
View File

@ -875,7 +875,32 @@ enum pmu_core_pwr_st {
#define MAX_WAIT_COUNT 1000
#define GRF_SOC_CON4 0x0e210
#define GRF_GPIO4C_IOMUX 0x0e028
#define GRF_GPIO2A_IOMUX 0xe000
#define GRF_GPIO2B_IOMUX 0xe004
#define GRF_GPIO2C_IOMUX 0xe008
#define GRF_GPIO2D_IOMUX 0xe00c
#define GRF_GPIO3A_IOMUX 0xe010
#define GRF_GPIO3B_IOMUX 0xe014
#define GRF_GPIO3C_IOMUX 0xe018
#define GRF_GPIO3D_IOMUX 0xe01c
#define GRF_GPIO4A_IOMUX 0xe020
#define GRF_GPIO4B_IOMUX 0xe024
#define GRF_GPIO4C_IOMUX 0xe028
#define GRF_GPIO4D_IOMUX 0xe02c
#define GRF_GPIO2A_P 0xe040
#define GRF_GPIO2B_P 0xe044
#define GRF_GPIO2C_P 0xe048
#define GRF_GPIO2D_P 0xe04C
#define GRF_GPIO3A_P 0xe050
#define GRF_GPIO3B_P 0xe054
#define GRF_GPIO3C_P 0xe058
#define GRF_GPIO3D_P 0xe05C
#define GRF_GPIO4A_P 0xe060
#define GRF_GPIO4B_P 0xe064
#define GRF_GPIO4C_P 0xe068
#define GRF_GPIO4D_P 0xe06C
#define PMUGRF_GPIO0A_SMT 0x0120
#define PMUGRF_SOC_CON0 0x0180

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