Browse Source
* changes: feat(stm32mp1): select platform compilation either by flag or DT feat(stm32mp1-fdts): add support for STM32MP13 DK board feat(stm32mp1-fdts): add DDR support for STM32MP13 feat(stm32mp1-fdts): add st-io_policies node for STM32MP13 feat(stm32mp1): updates for STM32MP13 device tree compilation feat(stm32mp1-fdts): add DT files for STM32MP13 feat(dt-bindings): add TZC400 bindings for STM32MP13 feat(stm32mp1): add "Boot mode" management for STM32MP13 feat(stm32mp1): manage HSLV on STM32MP13 feat(stm32mp1): add sdmmc compatible in platform define feat(st-sdmmc2): allow compatible to be defined in platform code feat(stm32mp1): update IO compensation on STM32MP13 feat(stm32mp1): call pmic_voltages_init() in platform init feat(st-pmic): add pmic_voltages_init() function feat(stm32mp1): update CFG0 OTP for STM32MP13 feat(stm32mp1): usb descriptor update for STM32MP13 feat(st-clock): add clock driver for STM32MP13 feat(dt-bindings): add bindings for STM32MP13 feat(stm32mp1): get CPU info from SYSCFG on STM32MP13 feat(stm32mp1): use only one filter for TZC400 on STM32MP13 feat(stm32mp1): add a second fixed regulator feat(stm32mp1): adaptations for STM32MP13 image header feat(stm32mp1): update boot API for header v2.0 feat(stm32mp1): update IP addresses for STM32MP13 feat(stm32mp1): add part numbers for STM32MP13 feat(stm32mp1): chip rev. Z is 0x1001 on STM32MP13 feat(stm32mp1): update BACKUP_BOOT_MODE for STM32MP13 feat(stm32mp1): stm32mp_is_single_core() for STM32MP13 feat(stm32mp1): remove unsupported features on STM32MP13 feat(stm32mp1): update memory mapping for STM32MP13 feat(stm32mp1): introduce new flag for STM32MP13 feat(st): update stm32image tool for header v2pull/1985/head
Manish Pandey
3 years ago
committed by
TrustedFirmware Code Review
TrustedFirmware Code Review
46 changed files with 12118 additions and 3056 deletions
File diff suppressed because it is too large
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved |
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* |
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* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
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*/ |
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|
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#ifndef CLK_STM32_CORE_H |
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#define CLK_STM32_CORE_H |
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struct mux_cfg { |
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uint16_t offset; |
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uint8_t shift; |
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uint8_t width; |
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uint8_t bitrdy; |
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}; |
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struct gate_cfg { |
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uint16_t offset; |
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uint8_t bit_idx; |
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uint8_t set_clr; |
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}; |
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struct clk_div_table { |
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unsigned int val; |
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unsigned int div; |
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}; |
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struct div_cfg { |
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uint16_t offset; |
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uint8_t shift; |
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uint8_t width; |
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uint8_t flags; |
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uint8_t bitrdy; |
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const struct clk_div_table *table; |
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}; |
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struct parent_cfg { |
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uint8_t num_parents; |
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const uint16_t *id_parents; |
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struct mux_cfg *mux; |
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}; |
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struct stm32_clk_priv; |
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struct stm32_clk_ops { |
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unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate); |
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int (*get_parent)(struct stm32_clk_priv *priv, int id); |
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int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate, |
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unsigned long prate); |
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int (*enable)(struct stm32_clk_priv *priv, int id); |
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void (*disable)(struct stm32_clk_priv *priv, int id); |
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bool (*is_enabled)(struct stm32_clk_priv *priv, int id); |
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void (*init)(struct stm32_clk_priv *priv, int id); |
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}; |
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struct clk_stm32 { |
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const char *name; |
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uint16_t binding; |
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uint16_t parent; |
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uint8_t flags; |
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void *clock_cfg; |
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const struct stm32_clk_ops *ops; |
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}; |
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struct stm32_clk_priv { |
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uintptr_t base; |
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const uint32_t num; |
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const struct clk_stm32 *clks; |
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const struct parent_cfg *parents; |
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const uint32_t nb_parents; |
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const struct gate_cfg *gates; |
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const uint32_t nb_gates; |
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const struct div_cfg *div; |
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const uint32_t nb_div; |
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struct clk_oscillator_data *osci_data; |
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const uint32_t nb_osci_data; |
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uint32_t *gate_refcounts; |
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void *pdata; |
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}; |
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struct stm32_clk_bypass { |
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uint16_t offset; |
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uint8_t bit_byp; |
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uint8_t bit_digbyp; |
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}; |
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struct stm32_clk_css { |
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uint16_t offset; |
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uint8_t bit_css; |
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}; |
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struct stm32_clk_drive { |
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uint16_t offset; |
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uint8_t drv_shift; |
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uint8_t drv_width; |
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uint8_t drv_default; |
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}; |
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struct clk_oscillator_data { |
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const char *name; |
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uint16_t id_clk; |
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unsigned long frequency; |
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uint16_t gate_id; |
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uint16_t gate_rdy_id; |
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struct stm32_clk_bypass *bypass; |
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struct stm32_clk_css *css; |
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struct stm32_clk_drive *drive; |
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}; |
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struct clk_fixed_rate { |
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const char *name; |
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unsigned long fixed_rate; |
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}; |
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struct clk_gate_cfg { |
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uint32_t offset; |
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uint8_t bit_idx; |
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}; |
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/* CLOCK FLAGS */ |
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#define CLK_IS_CRITICAL BIT(0) |
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#define CLK_IGNORE_UNUSED BIT(1) |
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#define CLK_SET_RATE_PARENT BIT(2) |
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#define CLK_DIVIDER_ONE_BASED BIT(0) |
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#define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
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#define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
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#define CLK_DIVIDER_HIWORD_MASK BIT(3) |
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#define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
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#define CLK_DIVIDER_READ_ONLY BIT(5) |
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#define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
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#define CLK_DIVIDER_BIG_ENDIAN BIT(7) |
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#define MUX_MAX_PARENTS U(0x8000) |
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#define MUX_PARENT_MASK GENMASK(14, 0) |
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#define MUX_FLAG U(0x8000) |
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#define MUX(mux) ((mux) | MUX_FLAG) |
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#define NO_GATE 0 |
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#define _NO_ID UINT16_MAX |
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#define CLK_IS_ROOT UINT16_MAX |
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#define MUX_NO_BIT_RDY UINT8_MAX |
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#define DIV_NO_BIT_RDY UINT8_MAX |
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#define MASK_WIDTH_SHIFT(_width, _shift) \ |
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GENMASK(((_width) + (_shift) - 1U), (_shift)) |
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int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base); |
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void clk_stm32_enable_critical_clocks(void); |
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struct stm32_clk_priv *clk_stm32_get_priv(void); |
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int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id); |
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const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id); |
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void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass); |
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void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv); |
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void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css); |
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int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on); |
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int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on); |
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int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id); |
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int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id); |
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const char *_clk_stm32_get_name(struct stm32_clk_priv *priv, int id); |
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const char *clk_stm32_get_name(struct stm32_clk_priv *priv, unsigned long binding_id); |
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int clk_stm32_get_counter(unsigned long binding_id); |
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void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); |
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int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id); |
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int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id); |
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int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel); |
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int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id); |
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int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx); |
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int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id); |
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unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id); |
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unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id); |
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bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag); |
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int _clk_stm32_enable(struct stm32_clk_priv *priv, int id); |
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void _clk_stm32_disable(struct stm32_clk_priv *priv, int id); |
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int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id); |
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void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id); |
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bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id); |
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int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id, |
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unsigned long rate, unsigned long parent_rate); |
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int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, |
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unsigned long prate); |
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unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, |
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int div_id, |
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unsigned long prate); |
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unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx, |
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unsigned long prate); |
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int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx); |
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void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx); |
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bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id); |
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bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx); |
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uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id); |
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int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value); |
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int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel); |
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int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id); |
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int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb); |
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#ifdef CFG_STM32_CLK_DEBUG |
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void clk_stm32_display_clock_info(void); |
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#endif |
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struct clk_stm32_div_cfg { |
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int id; |
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}; |
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#define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_binding),\ |
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.parent = (_parent),\ |
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.flags = (_flags),\ |
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.clock_cfg = &(struct clk_stm32_div_cfg){\ |
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.id = (_div_id),\ |
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},\ |
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.ops = &clk_stm32_divider_ops,\ |
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} |
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struct clk_stm32_gate_cfg { |
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int id; |
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}; |
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#define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_binding),\ |
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.parent = (_parent),\ |
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.flags = (_flags),\ |
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.clock_cfg = &(struct clk_stm32_gate_cfg){\ |
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.id = (_gate_id),\ |
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},\ |
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.ops = &clk_stm32_gate_ops,\ |
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} |
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struct fixed_factor_cfg { |
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unsigned int mult; |
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unsigned int div; |
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}; |
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unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, |
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int _idx, unsigned long prate); |
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#define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_idx),\ |
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.parent = (_parent),\ |
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.clock_cfg = &(struct fixed_factor_cfg){\ |
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.mult = (_mult),\ |
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.div = (_div),\ |
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},\ |
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.ops = &clk_fixed_factor_ops,\ |
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} |
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#define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_binding),\ |
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.parent = (_parent),\ |
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.flags = (_flags),\ |
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.clock_cfg = &(struct clk_gate_cfg){\ |
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.offset = (_offset),\ |
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.bit_idx = (_bit_idx),\ |
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},\ |
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.ops = &clk_gate_ops,\ |
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} |
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#define STM32_MUX(idx, _binding, _mux_id, _flags) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_binding),\ |
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.parent = (MUX(_mux_id)),\ |
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.flags = (_flags),\ |
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.clock_cfg = NULL,\ |
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.ops = (&clk_mux_ops),\ |
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} |
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struct clk_timer_cfg { |
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uint32_t apbdiv; |
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uint32_t timpre; |
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}; |
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#define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_idx),\ |
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.parent = (_parent),\ |
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.flags = (CLK_SET_RATE_PARENT | (_flags)),\ |
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.clock_cfg = &(struct clk_timer_cfg){\ |
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.apbdiv = (_apbdiv),\ |
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.timpre = (_timpre),\ |
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},\ |
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.ops = &clk_timer_ops,\ |
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} |
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struct clk_stm32_fixed_rate_cfg { |
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unsigned long rate; |
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}; |
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#define CLK_FIXED_RATE(idx, _binding, _rate) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_binding),\ |
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.parent = (CLK_IS_ROOT),\ |
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.clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ |
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.rate = (_rate),\ |
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},\ |
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.ops = &clk_stm32_fixed_rate_ops,\ |
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} |
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#define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\ |
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.offset = (_offset),\ |
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.bit_byp = (_bit_byp),\ |
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.bit_digbyp = (_bit_digbyp),\ |
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} |
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#define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ |
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.offset = (_offset),\ |
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.bit_css = (_bit_css),\ |
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} |
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#define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\ |
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.offset = (_offset),\ |
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.drv_shift = (_shift),\ |
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.drv_width = (_width),\ |
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.drv_default = (_default),\ |
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} |
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#define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ |
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[(idx_osc)] = (struct clk_oscillator_data){\ |
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.name = (_name),\ |
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.id_clk = (_id),\ |
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.gate_id = (_gate_id),\ |
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.gate_rdy_id = (_gate_rdy_id),\ |
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.bypass = (_bypass),\ |
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.css = (_css),\ |
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.drive = (_drive),\ |
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} |
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struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id); |
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void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id); |
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bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id); |
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int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id); |
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void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id); |
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struct stm32_osc_cfg { |
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int osc_id; |
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}; |
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#define CLK_OSC(idx, _idx, _parent, _osc_id) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_idx),\ |
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.parent = (_parent),\ |
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.flags = CLK_IS_CRITICAL,\ |
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.clock_cfg = &(struct stm32_osc_cfg){\ |
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.osc_id = (_osc_id),\ |
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},\ |
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.ops = &clk_stm32_osc_ops,\ |
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} |
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#define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ |
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[(idx)] = (struct clk_stm32){ \ |
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.name = #idx,\ |
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.binding = (_idx),\ |
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.parent = (_parent),\ |
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.flags = CLK_IS_CRITICAL,\ |
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.clock_cfg = &(struct stm32_osc_cfg){\ |
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.osc_id = (_osc_id),\ |
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},\ |
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.ops = &clk_stm32_osc_nogate_ops,\ |
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} |
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extern const struct stm32_clk_ops clk_mux_ops; |
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extern const struct stm32_clk_ops clk_stm32_divider_ops; |
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extern const struct stm32_clk_ops clk_stm32_gate_ops; |
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extern const struct stm32_clk_ops clk_fixed_factor_ops; |
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extern const struct stm32_clk_ops clk_gate_ops; |
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extern const struct stm32_clk_ops clk_timer_ops; |
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extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops; |
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extern const struct stm32_clk_ops clk_stm32_osc_ops; |
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extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops; |
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#endif /* CLK_STM32_CORE_H */ |
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File diff suppressed because it is too large
@ -0,0 +1,130 @@ |
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
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/* |
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
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*/ |
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/ { |
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aliases { |
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#if !STM32MP_EMMC && !STM32MP_SDMMC |
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/delete-property/ mmc0; |
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/delete-property/ mmc1; |
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#endif |
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/delete-property/ ethernet0; |
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/delete-property/ ethernet1; |
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}; |
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cpus { |
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cpu@0 { |
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/delete-property/ operating-points-v2; |
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}; |
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}; |
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/delete-node/ cpu0-opp-table; |
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/delete-node/ psci; |
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soc { |
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/delete-node/ sram@30000000; |
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/delete-node/ timer@40000000; |
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/delete-node/ timer@40001000; |
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/delete-node/ timer@40002000; |
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/delete-node/ timer@40003000; |
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/delete-node/ timer@40004000; |
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/delete-node/ timer@40005000; |
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/delete-node/ timer@40009000; |
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/delete-node/ spi@4000b000; |
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/delete-node/ audio-controller@4000b000; |
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/delete-node/ spi@4000c000; |
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/delete-node/ audio-controller@4000c000; |
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/delete-node/ audio-controller@4000d000; |
|||
/delete-node/ i2c@40012000; |
|||
/delete-node/ i2c@40013000; |
|||
/delete-node/ timer@44000000; |
|||
/delete-node/ timer@44001000; |
|||
/delete-node/ spi@44004000; |
|||
/delete-node/ audio-controller@44004000; |
|||
/delete-node/ sai@4400a000; |
|||
/delete-node/ sai@4400b000; |
|||
/delete-node/ dfsdm@4400d000; |
|||
/delete-node/ can@4400e000; |
|||
/delete-node/ can@4400f000; |
|||
/delete-node/ dma-controller@48000000; |
|||
/delete-node/ dma-controller@48001000; |
|||
/delete-node/ dma-router@48002000; |
|||
/delete-node/ adc@48003000; |
|||
/delete-node/ adc@48004000; |
|||
/delete-node/ dma@48005000; |
|||
/delete-node/ dma-router@48006000; |
|||
#if !STM32MP_USB_PROGRAMMER |
|||
/delete-node/ usb-otg@49000000; |
|||
#endif |
|||
/delete-node/ spi@4c002000; |
|||
/delete-node/ spi@4c003000; |
|||
/delete-node/ timer@4c007000; |
|||
/delete-node/ timer@4c008000; |
|||
/delete-node/ timer@4c009000; |
|||
/delete-node/ timer@4c00a000; |
|||
/delete-node/ timer@4c00b000; |
|||
/delete-node/ timer@4c00c000; |
|||
/delete-node/ timer@50021000; |
|||
/delete-node/ timer@50022000; |
|||
/delete-node/ timer@50023000; |
|||
/delete-node/ timer@50024000; |
|||
/delete-node/ vrefbuf@50025000; |
|||
/delete-node/ thermal@50028000; |
|||
/delete-node/ hdp@5002a000; |
|||
/delete-node/ dma-controller@58000000; |
|||
#if !STM32MP_RAW_NAND |
|||
/delete-node/ memory-controller@58002000; |
|||
#endif |
|||
#if !STM32MP_SPI_NAND && !STM32MP_SPI_NOR |
|||
/delete-node/ spi@58003000; |
|||
#endif |
|||
#if !STM32MP_EMMC && !STM32MP_SDMMC |
|||
/delete-node/ mmc@58005000; |
|||
/delete-node/ mmc@58007000; |
|||
#endif |
|||
/delete-node/ crc@58009000; |
|||
/delete-node/ stmmac-axi-config; |
|||
/delete-node/ eth1@5800a000; |
|||
#if !STM32MP_USB_PROGRAMMER |
|||
/delete-node/ usbh-ohci@5800c000; |
|||
/delete-node/ usbh-ehci@5800d000; |
|||
#endif |
|||
/delete-node/ eth2@5800e000; |
|||
/delete-node/ dcmipp@5a000000; |
|||
/delete-node/ display-controller@5a001000; |
|||
#if !STM32MP_USB_PROGRAMMER |
|||
/delete-node/ usbphyc@5a006000; |
|||
#endif |
|||
/delete-node/ perf@5a007000; |
|||
/delete-node/ rtc@5c004000; |
|||
/delete-node/ tamp@5c00a000; |
|||
/delete-node/ stgen@5c008000; |
|||
|
|||
pin-controller@50002000 { |
|||
#if !STM32MP_EMMC && !STM32MP_SDMMC |
|||
/delete-node/ sdmmc1-b4-0; |
|||
/delete-node/ sdmmc2-b4-0; |
|||
#endif |
|||
}; |
|||
}; |
|||
|
|||
/* |
|||
* UUID's here are UUID RFC 4122 compliant meaning fieds are stored in |
|||
* network order (big endian) |
|||
*/ |
|||
|
|||
st-io_policies { |
|||
fip-handles { |
|||
compatible = "st,io-fip-handle"; |
|||
fw_cfg_uuid = "5807e16a-8459-47be-8ed5-648e8dddab0e"; |
|||
bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38"; |
|||
bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288"; |
|||
bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9"; |
|||
bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4"; |
|||
hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc"; |
|||
tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021"; |
|||
nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9"; |
|||
}; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,184 @@ |
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
|||
/* |
|||
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
&ddr { |
|||
st,mem-name = DDR_MEM_NAME; |
|||
st,mem-speed = <DDR_MEM_SPEED>; |
|||
st,mem-size = <DDR_MEM_SIZE>; |
|||
|
|||
st,ctl-reg = < |
|||
DDR_MSTR |
|||
DDR_MRCTRL0 |
|||
DDR_MRCTRL1 |
|||
DDR_DERATEEN |
|||
DDR_DERATEINT |
|||
DDR_PWRCTL |
|||
DDR_PWRTMG |
|||
DDR_HWLPCTL |
|||
DDR_RFSHCTL0 |
|||
DDR_RFSHCTL3 |
|||
DDR_CRCPARCTL0 |
|||
DDR_ZQCTL0 |
|||
DDR_DFITMG0 |
|||
DDR_DFITMG1 |
|||
DDR_DFILPCFG0 |
|||
DDR_DFIUPD0 |
|||
DDR_DFIUPD1 |
|||
DDR_DFIUPD2 |
|||
DDR_DFIPHYMSTR |
|||
DDR_ODTMAP |
|||
DDR_DBG0 |
|||
DDR_DBG1 |
|||
DDR_DBGCMD |
|||
DDR_POISONCFG |
|||
DDR_PCCFG |
|||
>; |
|||
|
|||
st,ctl-timing = < |
|||
DDR_RFSHTMG |
|||
DDR_DRAMTMG0 |
|||
DDR_DRAMTMG1 |
|||
DDR_DRAMTMG2 |
|||
DDR_DRAMTMG3 |
|||
DDR_DRAMTMG4 |
|||
DDR_DRAMTMG5 |
|||
DDR_DRAMTMG6 |
|||
DDR_DRAMTMG7 |
|||
DDR_DRAMTMG8 |
|||
DDR_DRAMTMG14 |
|||
DDR_ODTCFG |
|||
>; |
|||
|
|||
st,ctl-map = < |
|||
DDR_ADDRMAP1 |
|||
DDR_ADDRMAP2 |
|||
DDR_ADDRMAP3 |
|||
DDR_ADDRMAP4 |
|||
DDR_ADDRMAP5 |
|||
DDR_ADDRMAP6 |
|||
DDR_ADDRMAP9 |
|||
DDR_ADDRMAP10 |
|||
DDR_ADDRMAP11 |
|||
>; |
|||
|
|||
st,ctl-perf = < |
|||
DDR_SCHED |
|||
DDR_SCHED1 |
|||
DDR_PERFHPR1 |
|||
DDR_PERFLPR1 |
|||
DDR_PERFWR1 |
|||
DDR_PCFGR_0 |
|||
DDR_PCFGW_0 |
|||
DDR_PCFGQOS0_0 |
|||
DDR_PCFGQOS1_0 |
|||
DDR_PCFGWQOS0_0 |
|||
DDR_PCFGWQOS1_0 |
|||
>; |
|||
|
|||
st,phy-reg = < |
|||
DDR_PGCR |
|||
DDR_ACIOCR |
|||
DDR_DXCCR |
|||
DDR_DSGCR |
|||
DDR_DCR |
|||
DDR_ODTCR |
|||
DDR_ZQ0CR1 |
|||
DDR_DX0GCR |
|||
DDR_DX1GCR |
|||
>; |
|||
|
|||
st,phy-timing = < |
|||
DDR_PTR0 |
|||
DDR_PTR1 |
|||
DDR_PTR2 |
|||
DDR_DTPR0 |
|||
DDR_DTPR1 |
|||
DDR_DTPR2 |
|||
DDR_MR0 |
|||
DDR_MR1 |
|||
DDR_MR2 |
|||
DDR_MR3 |
|||
>; |
|||
}; |
|||
|
|||
#undef DDR_MEM_NAME |
|||
#undef DDR_MEM_SPEED |
|||
#undef DDR_MEM_SIZE |
|||
#undef DDR_MSTR |
|||
#undef DDR_MRCTRL0 |
|||
#undef DDR_MRCTRL1 |
|||
#undef DDR_DERATEEN |
|||
#undef DDR_DERATEINT |
|||
#undef DDR_PWRCTL |
|||
#undef DDR_PWRTMG |
|||
#undef DDR_HWLPCTL |
|||
#undef DDR_RFSHCTL0 |
|||
#undef DDR_RFSHCTL3 |
|||
#undef DDR_RFSHTMG |
|||
#undef DDR_CRCPARCTL0 |
|||
#undef DDR_DRAMTMG0 |
|||
#undef DDR_DRAMTMG1 |
|||
#undef DDR_DRAMTMG2 |
|||
#undef DDR_DRAMTMG3 |
|||
#undef DDR_DRAMTMG4 |
|||
#undef DDR_DRAMTMG5 |
|||
#undef DDR_DRAMTMG6 |
|||
#undef DDR_DRAMTMG7 |
|||
#undef DDR_DRAMTMG8 |
|||
#undef DDR_DRAMTMG14 |
|||
#undef DDR_ZQCTL0 |
|||
#undef DDR_DFITMG0 |
|||
#undef DDR_DFITMG1 |
|||
#undef DDR_DFILPCFG0 |
|||
#undef DDR_DFIUPD0 |
|||
#undef DDR_DFIUPD1 |
|||
#undef DDR_DFIUPD2 |
|||
#undef DDR_DFIPHYMSTR |
|||
#undef DDR_ADDRMAP1 |
|||
#undef DDR_ADDRMAP2 |
|||
#undef DDR_ADDRMAP3 |
|||
#undef DDR_ADDRMAP4 |
|||
#undef DDR_ADDRMAP5 |
|||
#undef DDR_ADDRMAP6 |
|||
#undef DDR_ADDRMAP9 |
|||
#undef DDR_ADDRMAP10 |
|||
#undef DDR_ADDRMAP11 |
|||
#undef DDR_ODTCFG |
|||
#undef DDR_ODTMAP |
|||
#undef DDR_SCHED |
|||
#undef DDR_SCHED1 |
|||
#undef DDR_PERFHPR1 |
|||
#undef DDR_PERFLPR1 |
|||
#undef DDR_PERFWR1 |
|||
#undef DDR_DBG0 |
|||
#undef DDR_DBG1 |
|||
#undef DDR_DBGCMD |
|||
#undef DDR_POISONCFG |
|||
#undef DDR_PCCFG |
|||
#undef DDR_PCFGR_0 |
|||
#undef DDR_PCFGW_0 |
|||
#undef DDR_PCFGQOS0_0 |
|||
#undef DDR_PCFGQOS1_0 |
|||
#undef DDR_PCFGWQOS0_0 |
|||
#undef DDR_PCFGWQOS1_0 |
|||
#undef DDR_PGCR |
|||
#undef DDR_PTR0 |
|||
#undef DDR_PTR1 |
|||
#undef DDR_PTR2 |
|||
#undef DDR_ACIOCR |
|||
#undef DDR_DXCCR |
|||
#undef DDR_DSGCR |
|||
#undef DDR_DCR |
|||
#undef DDR_DTPR0 |
|||
#undef DDR_DTPR1 |
|||
#undef DDR_DTPR2 |
|||
#undef DDR_MR0 |
|||
#undef DDR_MR1 |
|||
#undef DDR_MR2 |
|||
#undef DDR_MR3 |
|||
#undef DDR_ODTCR |
|||
#undef DDR_ZQ0CR1 |
|||
#undef DDR_DX0GCR |
|||
#undef DDR_DX1GCR |
|||
@ -0,0 +1,100 @@ |
|||
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
|||
/* |
|||
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved |
|||
* |
|||
* STM32MP135C DISCO BOARD configuration |
|||
* 1x DDR3L 4Gb, 16-bit, 533MHz. |
|||
* Reference used MT41K256M16TW-107 P from Micron |
|||
* |
|||
* DDR type / Platform DDR3/3L |
|||
* freq 533MHz |
|||
* width 16 |
|||
* datasheet 1 |
|||
* DDR density 4 |
|||
* timing mode optimized |
|||
* Scheduling/QoS options : type = 6 |
|||
* address mapping : RBC |
|||
* Tc > + 85C : N |
|||
*/ |
|||
#define DDR_MEM_NAME "DDR3-1066 bin F 1x4Gb 533MHz v1.53" |
|||
#define DDR_MEM_SPEED 533000 |
|||
#define DDR_MEM_SIZE 0x20000000 |
|||
|
|||
#define DDR_MSTR 0x00040401 |
|||
#define DDR_MRCTRL0 0x00000010 |
|||
#define DDR_MRCTRL1 0x00000000 |
|||
#define DDR_DERATEEN 0x00000000 |
|||
#define DDR_DERATEINT 0x00800000 |
|||
#define DDR_PWRCTL 0x00000000 |
|||
#define DDR_PWRTMG 0x00400010 |
|||
#define DDR_HWLPCTL 0x00000000 |
|||
#define DDR_RFSHCTL0 0x00210000 |
|||
#define DDR_RFSHCTL3 0x00000000 |
|||
#define DDR_RFSHTMG 0x0081008B |
|||
#define DDR_CRCPARCTL0 0x00000000 |
|||
#define DDR_DRAMTMG0 0x121B2414 |
|||
#define DDR_DRAMTMG1 0x000A041B |
|||
#define DDR_DRAMTMG2 0x0607080F |
|||
#define DDR_DRAMTMG3 0x0050400C |
|||
#define DDR_DRAMTMG4 0x07040607 |
|||
#define DDR_DRAMTMG5 0x06060403 |
|||
#define DDR_DRAMTMG6 0x02020002 |
|||
#define DDR_DRAMTMG7 0x00000202 |
|||
#define DDR_DRAMTMG8 0x00001005 |
|||
#define DDR_DRAMTMG14 0x000000A0 |
|||
#define DDR_ZQCTL0 0xC2000040 |
|||
#define DDR_DFITMG0 0x02050105 |
|||
#define DDR_DFITMG1 0x00000202 |
|||
#define DDR_DFILPCFG0 0x07000000 |
|||
#define DDR_DFIUPD0 0xC0400003 |
|||
#define DDR_DFIUPD1 0x00000000 |
|||
#define DDR_DFIUPD2 0x00000000 |
|||
#define DDR_DFIPHYMSTR 0x00000000 |
|||
#define DDR_ADDRMAP1 0x00080808 |
|||
#define DDR_ADDRMAP2 0x00000000 |
|||
#define DDR_ADDRMAP3 0x00000000 |
|||
#define DDR_ADDRMAP4 0x00001F1F |
|||
#define DDR_ADDRMAP5 0x07070707 |
|||
#define DDR_ADDRMAP6 0x0F070707 |
|||
#define DDR_ADDRMAP9 0x00000000 |
|||
#define DDR_ADDRMAP10 0x00000000 |
|||
#define DDR_ADDRMAP11 0x00000000 |
|||
#define DDR_ODTCFG 0x06000600 |
|||
#define DDR_ODTMAP 0x00000001 |
|||
#define DDR_SCHED 0x00000F01 |
|||
#define DDR_SCHED1 0x00000000 |
|||
#define DDR_PERFHPR1 0x00000001 |
|||
#define DDR_PERFLPR1 0x04000200 |
|||
#define DDR_PERFWR1 0x08000400 |
|||
#define DDR_DBG0 0x00000000 |
|||
#define DDR_DBG1 0x00000000 |
|||
#define DDR_DBGCMD 0x00000000 |
|||
#define DDR_POISONCFG 0x00000000 |
|||
#define DDR_PCCFG 0x00000010 |
|||
#define DDR_PCFGR_0 0x00000000 |
|||
#define DDR_PCFGW_0 0x00000000 |
|||
#define DDR_PCFGQOS0_0 0x00100009 |
|||
#define DDR_PCFGQOS1_0 0x00000020 |
|||
#define DDR_PCFGWQOS0_0 0x01100B03 |
|||
#define DDR_PCFGWQOS1_0 0x01000200 |
|||
#define DDR_PGCR 0x01442E02 |
|||
#define DDR_PTR0 0x0022AA5B |
|||
#define DDR_PTR1 0x04841104 |
|||
#define DDR_PTR2 0x042DA068 |
|||
#define DDR_ACIOCR 0x10400812 |
|||
#define DDR_DXCCR 0x00000C40 |
|||
#define DDR_DSGCR 0xF200011F |
|||
#define DDR_DCR 0x0000000B |
|||
#define DDR_DTPR0 0x36D477D0 |
|||
#define DDR_DTPR1 0x098B00D8 |
|||
#define DDR_DTPR2 0x10023600 |
|||
#define DDR_MR0 0x00000830 |
|||
#define DDR_MR1 0x00000000 |
|||
#define DDR_MR2 0x00000208 |
|||
#define DDR_MR3 0x00000000 |
|||
#define DDR_ODTCR 0x00010000 |
|||
#define DDR_ZQ0CR1 0x00000038 |
|||
#define DDR_DX0GCR 0x0000CE81 |
|||
#define DDR_DX1GCR 0x0000CE81 |
|||
|
|||
#include "stm32mp13-ddr.dtsi" |
|||
@ -0,0 +1,55 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#include <common/tbbr/tbbr_img_def.h> |
|||
#include <dt-bindings/soc/stm32mp13-tzc400.h> |
|||
|
|||
#include <platform_def.h> |
|||
|
|||
#ifndef DDR_SIZE |
|||
#error "DDR_SIZE is not defined" |
|||
#endif |
|||
|
|||
#define DDR_NS_BASE STM32MP_DDR_BASE |
|||
#define DDR_SEC_SIZE 0x01e00000 |
|||
#define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE)) |
|||
#define DDR_SHARE_SIZE 0x00200000 |
|||
#define DDR_SHARE_BASE (DDR_SEC_BASE - DDR_SHARE_SIZE) |
|||
#define DDR_NS_SIZE (DDR_SHARE_BASE - DDR_NS_BASE) |
|||
|
|||
/dts-v1/; |
|||
|
|||
/ { |
|||
dtb-registry { |
|||
compatible = "fconf,dyn_cfg-dtb_registry"; |
|||
|
|||
hw-config { |
|||
load-address = <0x0 STM32MP_HW_CONFIG_BASE>; |
|||
max-size = <STM32MP_HW_CONFIG_MAX_SIZE>; |
|||
id = <HW_CONFIG_ID>; |
|||
}; |
|||
|
|||
nt_fw { |
|||
load-address = <0x0 STM32MP_BL33_BASE>; |
|||
max-size = <STM32MP_BL33_MAX_SIZE>; |
|||
id = <BL33_IMAGE_ID>; |
|||
}; |
|||
|
|||
tos_fw { |
|||
load-address = <0x0 DDR_SEC_BASE>; |
|||
max-size = <DDR_SEC_SIZE>; |
|||
id = <BL32_IMAGE_ID>; |
|||
}; |
|||
}; |
|||
|
|||
st-mem-firewall { |
|||
compatible = "st,mem-firewall"; |
|||
memory-ranges = < |
|||
DDR_NS_BASE DDR_NS_SIZE TZC_REGION_S_NONE TZC_REGION_NSEC_ALL_ACCESS_RDWR |
|||
DDR_SHARE_BASE DDR_SHARE_SIZE TZC_REGION_S_NONE |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
|||
DDR_SEC_BASE DDR_SEC_SIZE TZC_REGION_S_RDWR 0>; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,97 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> |
|||
*/ |
|||
#include <dt-bindings/pinctrl/stm32-pinfunc.h> |
|||
|
|||
&pinctrl { |
|||
i2c4_pins_a: i2c4-0 { |
|||
pins { |
|||
pinmux = <STM32_PINMUX('E', 15, AF6)>, /* I2C4_SCL */ |
|||
<STM32_PINMUX('B', 9, AF6)>; /* I2C4_SDA */ |
|||
bias-disable; |
|||
drive-open-drain; |
|||
slew-rate = <0>; |
|||
}; |
|||
}; |
|||
|
|||
sdmmc1_b4_pins_a: sdmmc1-b4-0 { |
|||
pins1 { |
|||
pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
|||
<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
|||
<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
|||
<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ |
|||
<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
|||
slew-rate = <1>; |
|||
drive-push-pull; |
|||
bias-disable; |
|||
}; |
|||
pins2 { |
|||
pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ |
|||
slew-rate = <2>; |
|||
drive-push-pull; |
|||
bias-disable; |
|||
}; |
|||
}; |
|||
|
|||
sdmmc2_b4_pins_a: sdmmc2-b4-0 { |
|||
pins1 { |
|||
pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ |
|||
<STM32_PINMUX('B', 15, AF10)>, /* SDMMC2_D1 */ |
|||
<STM32_PINMUX('B', 3, AF10)>, /* SDMMC2_D2 */ |
|||
<STM32_PINMUX('B', 4, AF10)>, /* SDMMC2_D3 */ |
|||
<STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
|||
slew-rate = <1>; |
|||
drive-push-pull; |
|||
bias-pull-up; |
|||
}; |
|||
pins2 { |
|||
pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ |
|||
slew-rate = <2>; |
|||
drive-push-pull; |
|||
bias-pull-up; |
|||
}; |
|||
}; |
|||
|
|||
uart4_pins_a: uart4-0 { |
|||
pins1 { |
|||
pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ |
|||
bias-disable; |
|||
drive-push-pull; |
|||
slew-rate = <0>; |
|||
}; |
|||
pins2 { |
|||
pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ |
|||
bias-disable; |
|||
}; |
|||
}; |
|||
|
|||
usart1_pins_a: usart1-0 { |
|||
pins1 { |
|||
pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ |
|||
<STM32_PINMUX('C', 2, AF7)>; /* USART1_RTS */ |
|||
bias-disable; |
|||
drive-push-pull; |
|||
slew-rate = <0>; |
|||
}; |
|||
pins2 { |
|||
pinmux = <STM32_PINMUX('B', 0, AF4)>, /* USART1_RX */ |
|||
<STM32_PINMUX('A', 7, AF7)>; /* USART1_CTS_NSS */ |
|||
bias-pull-up; |
|||
}; |
|||
}; |
|||
|
|||
uart8_pins_a: uart8-0 { |
|||
pins1 { |
|||
pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ |
|||
bias-disable; |
|||
drive-push-pull; |
|||
slew-rate = <0>; |
|||
}; |
|||
pins2 { |
|||
pinmux = <STM32_PINMUX('F', 9, AF8)>; /* UART8_RX */ |
|||
bias-pull-up; |
|||
}; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,621 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
#include <dt-bindings/clock/stm32mp13-clks.h> |
|||
#include <dt-bindings/interrupt-controller/arm-gic.h> |
|||
#include <dt-bindings/reset/stm32mp13-resets.h> |
|||
|
|||
/ { |
|||
#address-cells = <1>; |
|||
#size-cells = <1>; |
|||
|
|||
cpus { |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
|
|||
cpu0: cpu@0 { |
|||
compatible = "arm,cortex-a7"; |
|||
device_type = "cpu"; |
|||
reg = <0>; |
|||
clocks = <&rcc CK_MPU>; |
|||
clock-names = "cpu"; |
|||
nvmem-cells = <&part_number_otp>; |
|||
nvmem-cell-names = "part_number"; |
|||
}; |
|||
}; |
|||
|
|||
nvmem_layout: nvmem_layout@0 { |
|||
compatible = "st,stm32-nvmem-layout"; |
|||
|
|||
nvmem-cells = <&cfg0_otp>, |
|||
<&part_number_otp>, |
|||
<&monotonic_otp>, |
|||
<&nand_otp>, |
|||
<&nand2_otp>, |
|||
<&uid_otp>, |
|||
<&hw2_otp>; |
|||
|
|||
nvmem-cell-names = "cfg0_otp", |
|||
"part_number_otp", |
|||
"monotonic_otp", |
|||
"nand_otp", |
|||
"nand2_otp", |
|||
"uid_otp", |
|||
"hw2_otp"; |
|||
}; |
|||
|
|||
clocks { |
|||
clk_csi: clk-csi { |
|||
#clock-cells = <0>; |
|||
compatible = "fixed-clock"; |
|||
clock-frequency = <4000000>; |
|||
}; |
|||
|
|||
clk_hse: clk-hse { |
|||
#clock-cells = <0>; |
|||
compatible = "fixed-clock"; |
|||
clock-frequency = <24000000>; |
|||
}; |
|||
|
|||
clk_hsi: clk-hsi { |
|||
#clock-cells = <0>; |
|||
compatible = "fixed-clock"; |
|||
clock-frequency = <64000000>; |
|||
}; |
|||
|
|||
clk_lse: clk-lse { |
|||
#clock-cells = <0>; |
|||
compatible = "fixed-clock"; |
|||
clock-frequency = <32768>; |
|||
}; |
|||
|
|||
clk_lsi: clk-lsi { |
|||
#clock-cells = <0>; |
|||
compatible = "fixed-clock"; |
|||
clock-frequency = <32000>; |
|||
}; |
|||
}; |
|||
|
|||
intc: interrupt-controller@a0021000 { |
|||
compatible = "arm,cortex-a7-gic"; |
|||
#interrupt-cells = <3>; |
|||
interrupt-controller; |
|||
reg = <0xa0021000 0x1000>, |
|||
<0xa0022000 0x2000>; |
|||
}; |
|||
|
|||
psci { |
|||
compatible = "arm,psci-1.0"; |
|||
method = "smc"; |
|||
}; |
|||
|
|||
soc { |
|||
compatible = "simple-bus"; |
|||
#address-cells = <1>; |
|||
#size-cells = <1>; |
|||
interrupt-parent = <&intc>; |
|||
ranges; |
|||
|
|||
usart3: serial@4000f000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x4000f000 0x400>; |
|||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc USART3_K>; |
|||
resets = <&rcc USART3_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
uart4: serial@40010000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x40010000 0x400>; |
|||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc UART4_K>; |
|||
resets = <&rcc UART4_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
uart5: serial@40011000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x40011000 0x400>; |
|||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc UART5_K>; |
|||
resets = <&rcc UART5_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
uart7: serial@40018000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x40018000 0x400>; |
|||
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc UART7_K>; |
|||
resets = <&rcc UART7_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
uart8: serial@40019000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x40019000 0x400>; |
|||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc UART8_K>; |
|||
resets = <&rcc UART8_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
usart6: serial@44003000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x44003000 0x400>; |
|||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc USART6_K>; |
|||
resets = <&rcc USART6_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
usbotg_hs: usb-otg@49000000 { |
|||
compatible = "st,stm32mp15-hsotg", "snps,dwc2"; |
|||
reg = <0x49000000 0x40000>; |
|||
clocks = <&rcc USBO_K>; |
|||
clock-names = "otg"; |
|||
resets = <&rcc USBO_R>; |
|||
reset-names = "dwc2"; |
|||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
|||
g-rx-fifo-size = <512>; |
|||
g-np-tx-fifo-size = <32>; |
|||
g-tx-fifo-size = <256 16 16 16 16 16 16 16>; |
|||
dr_mode = "otg"; |
|||
usb33d-supply = <&usb33>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
usart1: serial@4c000000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x4c000000 0x400>; |
|||
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc USART1_K>; |
|||
resets = <&rcc USART1_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
usart2: serial@4c001000 { |
|||
compatible = "st,stm32h7-uart"; |
|||
reg = <0x4c001000 0x400>; |
|||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc USART2_K>; |
|||
resets = <&rcc USART2_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
i2c3: i2c@4c004000 { |
|||
compatible = "st,stm32mp13-i2c"; |
|||
reg = <0x4c004000 0x400>; |
|||
interrupt-names = "event", "error"; |
|||
interrupts-extended = <&exti 23 IRQ_TYPE_LEVEL_HIGH>, |
|||
<&intc GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc I2C3_K>; |
|||
resets = <&rcc I2C3_R>; |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
st,syscfg-fmp = <&syscfg 0x4 0x4>; |
|||
i2c-analog-filter; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
i2c4: i2c@4c005000 { |
|||
compatible = "st,stm32mp13-i2c"; |
|||
reg = <0x4c005000 0x400>; |
|||
interrupt-names = "event", "error"; |
|||
interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>, |
|||
<&intc GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc I2C4_K>; |
|||
resets = <&rcc I2C4_R>; |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
st,syscfg-fmp = <&syscfg 0x4 0x8>; |
|||
i2c-analog-filter; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
i2c5: i2c@4c006000 { |
|||
compatible = "st,stm32mp13-i2c"; |
|||
reg = <0x4c006000 0x400>; |
|||
interrupt-names = "event", "error"; |
|||
interrupts-extended = <&exti 25 IRQ_TYPE_LEVEL_HIGH>, |
|||
<&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc I2C5_K>; |
|||
resets = <&rcc I2C5_R>; |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
st,syscfg-fmp = <&syscfg 0x4 0x10>; |
|||
i2c-analog-filter; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
rcc: rcc@50000000 { |
|||
compatible = "st,stm32mp13-rcc", "syscon"; |
|||
reg = <0x50000000 0x1000>; |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
#clock-cells = <1>; |
|||
#reset-cells = <1>; |
|||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
|||
secure-interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
|||
secure-interrupt-names = "wakeup"; |
|||
}; |
|||
|
|||
pwr_regulators: pwr@50001000 { |
|||
compatible = "st,stm32mp1,pwr-reg"; |
|||
reg = <0x50001000 0x10>; |
|||
|
|||
reg11: reg11 { |
|||
regulator-name = "reg11"; |
|||
regulator-min-microvolt = <1100000>; |
|||
regulator-max-microvolt = <1100000>; |
|||
}; |
|||
|
|||
reg18: reg18 { |
|||
regulator-name = "reg18"; |
|||
regulator-min-microvolt = <1800000>; |
|||
regulator-max-microvolt = <1800000>; |
|||
}; |
|||
|
|||
usb33: usb33 { |
|||
regulator-name = "usb33"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
}; |
|||
}; |
|||
|
|||
exti: interrupt-controller@5000d000 { |
|||
compatible = "st,stm32mp13-exti", "syscon"; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x5000d000 0x400>; |
|||
}; |
|||
|
|||
syscfg: syscon@50020000 { |
|||
compatible = "st,stm32mp157-syscfg", "syscon"; |
|||
reg = <0x50020000 0x400>; |
|||
clocks = <&rcc SYSCFG>; |
|||
}; |
|||
|
|||
vrefbuf: vrefbuf@50025000 { |
|||
compatible = "st,stm32-vrefbuf"; |
|||
reg = <0x50025000 0x8>; |
|||
regulator-min-microvolt = <1500000>; |
|||
regulator-max-microvolt = <2500000>; |
|||
clocks = <&rcc VREF>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
hash: hash@54003000 { |
|||
compatible = "st,stm32mp13-hash"; |
|||
reg = <0x54003000 0x400>; |
|||
clocks = <&rcc HASH1>; |
|||
resets = <&rcc HASH1_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
rng: rng@54004000 { |
|||
compatible = "st,stm32mp13-rng"; |
|||
reg = <0x54004000 0x400>; |
|||
clocks = <&rcc RNG1_K>; |
|||
resets = <&rcc RNG1_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
fmc: memory-controller@58002000 { |
|||
#address-cells = <2>; |
|||
#size-cells = <1>; |
|||
compatible = "st,stm32mp1-fmc2-ebi"; |
|||
reg = <0x58002000 0x1000>; |
|||
clocks = <&rcc FMC_K>; |
|||
resets = <&rcc FMC_R>; |
|||
status = "disabled"; |
|||
|
|||
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ |
|||
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */ |
|||
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */ |
|||
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ |
|||
<4 0 0x80000000 0x10000000>; /* NAND */ |
|||
|
|||
nand-controller@4,0 { |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
compatible = "st,stm32mp1-fmc2-nfc"; |
|||
reg = <4 0x00000000 0x1000>, |
|||
<4 0x08010000 0x1000>, |
|||
<4 0x08020000 0x1000>, |
|||
<4 0x01000000 0x1000>, |
|||
<4 0x09010000 0x1000>, |
|||
<4 0x09020000 0x1000>; |
|||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
|||
status = "disabled"; |
|||
}; |
|||
}; |
|||
|
|||
qspi: spi@58003000 { |
|||
compatible = "st,stm32f469-qspi"; |
|||
reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; |
|||
reg-names = "qspi", "qspi_mm"; |
|||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc QSPI_K>; |
|||
resets = <&rcc QSPI_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
sdmmc1: mmc@58005000 { |
|||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; |
|||
arm,primecell-periphid = <0x20253180>; |
|||
reg = <0x58005000 0x1000>, <0x58006000 0x1000>; |
|||
clocks = <&rcc SDMMC1_K>; |
|||
clock-names = "apb_pclk"; |
|||
resets = <&rcc SDMMC1_R>; |
|||
cap-sd-highspeed; |
|||
cap-mmc-highspeed; |
|||
max-frequency = <120000000>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
sdmmc2: mmc@58007000 { |
|||
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; |
|||
arm,primecell-periphid = <0x20253180>; |
|||
reg = <0x58007000 0x1000>, <0x58008000 0x1000>; |
|||
clocks = <&rcc SDMMC2_K>; |
|||
clock-names = "apb_pclk"; |
|||
resets = <&rcc SDMMC2_R>; |
|||
cap-sd-highspeed; |
|||
cap-mmc-highspeed; |
|||
max-frequency = <120000000>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
crc1: crc@58009000 { |
|||
compatible = "st,stm32f7-crc"; |
|||
reg = <0x58009000 0x400>; |
|||
clocks = <&rcc CRC1>; |
|||
}; |
|||
|
|||
usbh_ohci: usbh-ohci@5800c000 { |
|||
compatible = "generic-ohci"; |
|||
reg = <0x5800c000 0x1000>; |
|||
clocks = <&rcc USBH>; |
|||
resets = <&rcc USBH_R>; |
|||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
usbh_ehci: usbh-ehci@5800d000 { |
|||
compatible = "generic-ehci"; |
|||
reg = <0x5800d000 0x1000>; |
|||
clocks = <&rcc USBH>; |
|||
resets = <&rcc USBH_R>; |
|||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
|||
companion = <&usbh_ohci>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
iwdg2: watchdog@5a002000 { |
|||
compatible = "st,stm32mp1-iwdg"; |
|||
reg = <0x5a002000 0x400>; |
|||
clocks = <&rcc IWDG2>, <&rcc CK_LSI>; |
|||
clock-names = "pclk", "lsi"; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
ddr: ddr@5a003000{ |
|||
compatible = "st,stm32mp13-ddr"; |
|||
reg = <0x5a003000 0x550>, <0x5a004000 0x234>; |
|||
clocks = <&rcc AXIDCG>, |
|||
<&rcc DDRC1>, |
|||
<&rcc DDRPHYC>, |
|||
<&rcc DDRCAPB>, |
|||
<&rcc DDRPHYCAPB>; |
|||
clock-names = "axidcg", |
|||
"ddrc1", |
|||
"ddrphyc", |
|||
"ddrcapb", |
|||
"ddrphycapb"; |
|||
}; |
|||
|
|||
usbphyc: usbphyc@5a006000 { |
|||
#address-cells = <1>; |
|||
#size-cells = <0>; |
|||
#clock-cells = <0>; |
|||
compatible = "st,stm32mp1-usbphyc"; |
|||
reg = <0x5a006000 0x1000>; |
|||
clocks = <&rcc USBPHY_K>; |
|||
resets = <&rcc USBPHY_R>; |
|||
vdda1v1-supply = <®11>; |
|||
vdda1v8-supply = <®18>; |
|||
status = "disabled"; |
|||
|
|||
usbphyc_port0: usb-phy@0 { |
|||
#phy-cells = <0>; |
|||
reg = <0>; |
|||
}; |
|||
|
|||
usbphyc_port1: usb-phy@1 { |
|||
#phy-cells = <1>; |
|||
reg = <1>; |
|||
}; |
|||
}; |
|||
|
|||
iwdg1: watchdog@5c003000 { |
|||
compatible = "st,stm32mp1-iwdg"; |
|||
reg = <0x5c003000 0x400>; |
|||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc IWDG1>, <&rcc CK_LSI>; |
|||
clock-names = "pclk", "lsi"; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
bsec: efuse@5c005000 { |
|||
compatible = "st,stm32mp15-bsec"; |
|||
reg = <0x5c005000 0x400>; |
|||
#address-cells = <1>; |
|||
#size-cells = <1>; |
|||
|
|||
cfg0_otp: cfg0_otp@0 { |
|||
reg = <0x0 0x2>; |
|||
}; |
|||
part_number_otp: part_number_otp@4 { |
|||
reg = <0x4 0x2>; |
|||
}; |
|||
monotonic_otp: monotonic_otp@10 { |
|||
reg = <0x10 0x4>; |
|||
}; |
|||
nand_otp: cfg9_otp@24 { |
|||
reg = <0x24 0x4>; |
|||
}; |
|||
nand2_otp: cfg10_otp@28 { |
|||
reg = <0x28 0x4>; |
|||
}; |
|||
uid_otp: uid_otp@34 { |
|||
reg = <0x34 0xc>; |
|||
}; |
|||
hw2_otp: hw2_otp@48 { |
|||
reg = <0x48 0x4>; |
|||
}; |
|||
ts_cal1: calib@5c { |
|||
reg = <0x5c 0x2>; |
|||
}; |
|||
ts_cal2: calib@5e { |
|||
reg = <0x5e 0x2>; |
|||
}; |
|||
pkh_otp: pkh_otp@60 { |
|||
reg = <0x60 0x20>; |
|||
}; |
|||
mac_addr: mac_addr@e4 { |
|||
reg = <0xe4 0xc>; |
|||
st,non-secure-otp; |
|||
}; |
|||
}; |
|||
|
|||
tamp: tamp@5c00a000 { |
|||
reg = <0x5c00a000 0x400>; |
|||
}; |
|||
|
|||
/* |
|||
* Break node order to solve dependency probe issue between |
|||
* pinctrl and exti. |
|||
*/ |
|||
pinctrl: pin-controller@50002000 { |
|||
#address-cells = <1>; |
|||
#size-cells = <1>; |
|||
compatible = "st,stm32mp135-pinctrl"; |
|||
ranges = <0 0x50002000 0x8400>; |
|||
interrupt-parent = <&exti>; |
|||
st,syscfg = <&exti 0x60 0xff>; |
|||
pins-are-numbered; |
|||
|
|||
gpioa: gpio@50002000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x0 0x400>; |
|||
clocks = <&rcc GPIOA>; |
|||
st,bank-name = "GPIOA"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 0 16>; |
|||
}; |
|||
|
|||
gpiob: gpio@50003000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x1000 0x400>; |
|||
clocks = <&rcc GPIOB>; |
|||
st,bank-name = "GPIOB"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 16 16>; |
|||
}; |
|||
|
|||
gpioc: gpio@50004000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x2000 0x400>; |
|||
clocks = <&rcc GPIOC>; |
|||
st,bank-name = "GPIOC"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 32 16>; |
|||
}; |
|||
|
|||
gpiod: gpio@50005000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x3000 0x400>; |
|||
clocks = <&rcc GPIOD>; |
|||
st,bank-name = "GPIOD"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 48 16>; |
|||
}; |
|||
|
|||
gpioe: gpio@50006000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x4000 0x400>; |
|||
clocks = <&rcc GPIOE>; |
|||
st,bank-name = "GPIOE"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 64 16>; |
|||
}; |
|||
|
|||
gpiof: gpio@50007000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x5000 0x400>; |
|||
clocks = <&rcc GPIOF>; |
|||
st,bank-name = "GPIOF"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 80 16>; |
|||
}; |
|||
|
|||
gpiog: gpio@50008000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x6000 0x400>; |
|||
clocks = <&rcc GPIOG>; |
|||
st,bank-name = "GPIOG"; |
|||
ngpios = <16>; |
|||
gpio-ranges = <&pinctrl 0 96 16>; |
|||
}; |
|||
|
|||
gpioh: gpio@50009000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x7000 0x400>; |
|||
clocks = <&rcc GPIOH>; |
|||
st,bank-name = "GPIOH"; |
|||
ngpios = <15>; |
|||
gpio-ranges = <&pinctrl 0 112 15>; |
|||
}; |
|||
|
|||
gpioi: gpio@5000a000 { |
|||
gpio-controller; |
|||
#gpio-cells = <2>; |
|||
interrupt-controller; |
|||
#interrupt-cells = <2>; |
|||
reg = <0x8000 0x400>; |
|||
clocks = <&rcc GPIOI>; |
|||
st,bank-name = "GPIOI"; |
|||
ngpios = <8>; |
|||
gpio-ranges = <&pinctrl 0 128 8>; |
|||
}; |
|||
}; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,21 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#include "stm32mp131.dtsi" |
|||
|
|||
/ { |
|||
soc { |
|||
m_can1: can@4400e000 { |
|||
reg = <0x4400e000 0x400>, <0x44011000 0x1400>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
m_can2: can@4400f000 { |
|||
reg = <0x4400f000 0x400>, <0x44011000 0x2800>; |
|||
status = "disabled"; |
|||
}; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,12 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#include "stm32mp133.dtsi" |
|||
|
|||
/ { |
|||
soc { |
|||
}; |
|||
}; |
|||
@ -0,0 +1,7 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (c) 2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#define DDR_SIZE 0x20000000 /* 512MB */ |
|||
#include "stm32mp13-fw-config.dtsi" |
|||
@ -0,0 +1,353 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
/dts-v1/; |
|||
|
|||
#include <dt-bindings/clock/stm32mp13-clksrc.h> |
|||
#include "stm32mp135.dtsi" |
|||
#include "stm32mp13xf.dtsi" |
|||
#include "stm32mp13-ddr3-1x4Gb-1066-binF.dtsi" |
|||
#include "stm32mp13-pinctrl.dtsi" |
|||
|
|||
/ { |
|||
model = "STMicroelectronics STM32MP135F-DK Discovery Board"; |
|||
compatible = "st,stm32mp135f-dk", "st,stm32mp135"; |
|||
|
|||
aliases { |
|||
serial0 = &uart4; |
|||
serial1 = &usart1; |
|||
serial2 = &uart8; |
|||
serial3 = &usart2; |
|||
}; |
|||
|
|||
chosen { |
|||
stdout-path = "serial0:115200n8"; |
|||
}; |
|||
|
|||
memory@c0000000 { |
|||
device_type = "memory"; |
|||
reg = <0xc0000000 0x20000000>; |
|||
}; |
|||
|
|||
vin: vin { |
|||
compatible = "regulator-fixed"; |
|||
regulator-name = "vin"; |
|||
regulator-min-microvolt = <5000000>; |
|||
regulator-max-microvolt = <5000000>; |
|||
regulator-always-on; |
|||
}; |
|||
|
|||
v3v3_ao: v3v3_ao { |
|||
compatible = "regulator-fixed"; |
|||
regulator-name = "v3v3_ao"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
regulator-always-on; |
|||
}; |
|||
}; |
|||
|
|||
&bsec { |
|||
board_id: board_id@f0 { |
|||
reg = <0xf0 0x4>; |
|||
st,non-secure-otp; |
|||
}; |
|||
}; |
|||
|
|||
&cpu0 { |
|||
cpu-supply = <&vddcpu>; |
|||
}; |
|||
|
|||
&hash { |
|||
status = "okay"; |
|||
}; |
|||
|
|||
&i2c4 { |
|||
pinctrl-names = "default"; |
|||
pinctrl-0 = <&i2c4_pins_a>; |
|||
i2c-scl-rising-time-ns = <185>; |
|||
i2c-scl-falling-time-ns = <20>; |
|||
clock-frequency = <400000>; |
|||
status = "disabled"; |
|||
secure-status = "okay"; |
|||
|
|||
pmic: stpmic@33 { |
|||
compatible = "st,stpmic1"; |
|||
reg = <0x33>; |
|||
|
|||
status = "disabled"; |
|||
secure-status = "okay"; |
|||
|
|||
regulators { |
|||
compatible = "st,stpmic1-regulators"; |
|||
buck1-supply = <&vin>; |
|||
buck2-supply = <&vin>; |
|||
buck3-supply = <&vin>; |
|||
buck4-supply = <&vin>; |
|||
ldo1-supply = <&vin>; |
|||
ldo4-supply = <&vin>; |
|||
ldo5-supply = <&vin>; |
|||
ldo6-supply = <&vin>; |
|||
vref_ddr-supply = <&vin>; |
|||
pwr_sw1-supply = <&bst_out>; |
|||
pwr_sw2-supply = <&v3v3_ao>; |
|||
|
|||
vddcpu: buck1 { |
|||
regulator-name = "vddcpu"; |
|||
regulator-min-microvolt = <1250000>; |
|||
regulator-max-microvolt = <1250000>; |
|||
regulator-always-on; |
|||
regulator-over-current-protection; |
|||
}; |
|||
|
|||
vdd_ddr: buck2 { |
|||
regulator-name = "vdd_ddr"; |
|||
regulator-min-microvolt = <1350000>; |
|||
regulator-max-microvolt = <1350000>; |
|||
regulator-always-on; |
|||
regulator-over-current-protection; |
|||
}; |
|||
|
|||
vdd: buck3 { |
|||
regulator-name = "vdd"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
regulator-always-on; |
|||
st,mask-reset; |
|||
regulator-over-current-protection; |
|||
}; |
|||
|
|||
vddcore: buck4 { |
|||
regulator-name = "vddcore"; |
|||
regulator-min-microvolt = <1250000>; |
|||
regulator-max-microvolt = <1250000>; |
|||
regulator-always-on; |
|||
regulator-over-current-protection; |
|||
}; |
|||
|
|||
vdd_adc: ldo1 { |
|||
regulator-name = "vdd_adc"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
}; |
|||
|
|||
vdd_usb: ldo4 { |
|||
regulator-name = "vdd_usb"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
}; |
|||
|
|||
vdd_sd: ldo5 { |
|||
regulator-name = "vdd_sd"; |
|||
regulator-min-microvolt = <3300000>; |
|||
regulator-max-microvolt = <3300000>; |
|||
regulator-boot-on; |
|||
}; |
|||
|
|||
v1v8_periph: ldo6 { |
|||
regulator-name = "v1v8_periph"; |
|||
regulator-min-microvolt = <1800000>; |
|||
regulator-max-microvolt = <1800000>; |
|||
}; |
|||
|
|||
vref_ddr: vref_ddr { |
|||
regulator-name = "vref_ddr"; |
|||
regulator-always-on; |
|||
}; |
|||
|
|||
bst_out: boost { |
|||
regulator-name = "bst_out"; |
|||
}; |
|||
|
|||
v3v3_sw: pwr_sw2 { |
|||
regulator-name = "v3v3_sw"; |
|||
regulator-active-discharge = <1>; |
|||
regulator-always-on; |
|||
}; |
|||
}; |
|||
}; |
|||
}; |
|||
|
|||
&iwdg2 { |
|||
timeout-sec = <32>; |
|||
status = "okay"; |
|||
}; |
|||
|
|||
&nvmem_layout { |
|||
nvmem-cells = <&cfg0_otp>, |
|||
<&part_number_otp>, |
|||
<&monotonic_otp>, |
|||
<&nand_otp>, |
|||
<&nand2_otp>, |
|||
<&uid_otp>, |
|||
<&hw2_otp>, |
|||
<&pkh_otp>, |
|||
<&board_id>; |
|||
|
|||
nvmem-cell-names = "cfg0_otp", |
|||
"part_number_otp", |
|||
"monotonic_otp", |
|||
"nand_otp", |
|||
"nand2_otp", |
|||
"uid_otp", |
|||
"hw2_otp", |
|||
"pkh_otp", |
|||
"board_id"; |
|||
}; |
|||
|
|||
&pka { |
|||
secure-status = "okay"; |
|||
}; |
|||
|
|||
&pwr_regulators { |
|||
vdd-supply = <&vdd>; |
|||
vdd_3v3_usbfs-supply = <&vdd_usb>; |
|||
}; |
|||
|
|||
&rcc { |
|||
st,clksrc = < |
|||
CLK_MPU_PLL1P |
|||
CLK_AXI_PLL2P |
|||
CLK_MLAHBS_PLL3 |
|||
CLK_CKPER_HSE |
|||
CLK_RTC_LSE |
|||
CLK_SDMMC1_PLL4P |
|||
CLK_SDMMC2_PLL4P |
|||
CLK_STGEN_HSE |
|||
CLK_USBPHY_HSE |
|||
CLK_I2C4_HSI |
|||
CLK_USBO_USBPHY |
|||
CLK_I2C12_HSI |
|||
CLK_UART2_HSI |
|||
CLK_UART4_HSI |
|||
CLK_SAES_AXI |
|||
>; |
|||
|
|||
st,clkdiv = < |
|||
DIV(DIV_AXI, 0) |
|||
DIV(DIV_MLAHB, 0) |
|||
DIV(DIV_APB1, 1) |
|||
DIV(DIV_APB2, 1) |
|||
DIV(DIV_APB3, 1) |
|||
DIV(DIV_APB4, 1) |
|||
DIV(DIV_APB5, 2) |
|||
DIV(DIV_APB6, 1) |
|||
DIV(DIV_RTC, 0) |
|||
>; |
|||
|
|||
st,pll_vco { |
|||
pll1_vco_1300Mhz: pll1-vco-1300Mhz { |
|||
src = < CLK_PLL12_HSE >; |
|||
divmn = < 2 80 >; |
|||
frac = < 0x800 >; |
|||
}; |
|||
|
|||
pll2_vco_1066Mhz: pll2-vco-1066Mhz { |
|||
src = < CLK_PLL12_HSE >; |
|||
divmn = < 2 65 >; |
|||
frac = < 0x1400 >; |
|||
}; |
|||
|
|||
pll3_vco_417_8Mhz: pll2-vco-417_8Mhz { |
|||
src = < CLK_PLL3_HSE >; |
|||
divmn = < 1 33 >; |
|||
frac = < 0x1a04 >; |
|||
}; |
|||
|
|||
pll4_vco_600Mhz: pll2-vco-600Mhz { |
|||
src = < CLK_PLL4_HSE >; |
|||
divmn = < 1 49 >; |
|||
}; |
|||
}; |
|||
|
|||
/* VCO = 1300.0 MHz => P = 650 (CPU) */ |
|||
pll1:st,pll@0 { |
|||
compatible = "st,stm32mp1-pll"; |
|||
reg = <0>; |
|||
|
|||
st,pll = < &pll1_cfg1 >; |
|||
|
|||
pll1_cfg1: pll1_cfg1 { |
|||
st,pll_vco = < &pll1_vco_1300Mhz >; |
|||
st,pll_div_pqr = < 0 1 1 >; |
|||
}; |
|||
}; |
|||
|
|||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ |
|||
pll2:st,pll@1 { |
|||
compatible = "st,stm32mp1-pll"; |
|||
reg = <1>; |
|||
|
|||
st,pll = < &pll2_cfg1 >; |
|||
|
|||
pll2_cfg1: pll2_cfg1 { |
|||
st,pll_vco = < &pll2_vco_1066Mhz >; |
|||
st,pll_div_pqr = < 1 1 0 >; |
|||
}; |
|||
}; |
|||
|
|||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 209 */ |
|||
pll3:st,pll@2 { |
|||
compatible = "st,stm32mp1-pll"; |
|||
reg = <2>; |
|||
|
|||
st,pll = < &pll3_cfg1 >; |
|||
|
|||
pll3_cfg1: pll3_cfg1 { |
|||
st,pll_vco = < &pll3_vco_417_8Mhz >; |
|||
st,pll_div_pqr = < 1 16 1 >; |
|||
}; |
|||
}; |
|||
|
|||
/* VCO = 600.0 MHz => P = 50, Q = 10, R = 100 */ |
|||
pll4:st,pll@3 { |
|||
compatible = "st,stm32mp1-pll"; |
|||
reg = <3>; |
|||
|
|||
st,pll = < &pll4_cfg1 >; |
|||
|
|||
pll4_cfg1: pll4_cfg1 { |
|||
st,pll_vco = < &pll4_vco_600Mhz >; |
|||
st,pll_div_pqr = < 11 59 5 >; |
|||
}; |
|||
}; |
|||
}; |
|||
|
|||
&rng { |
|||
status = "okay"; |
|||
}; |
|||
|
|||
&saes { |
|||
secure-status = "okay"; |
|||
}; |
|||
|
|||
&sdmmc1 { |
|||
pinctrl-names = "default"; |
|||
pinctrl-0 = <&sdmmc1_b4_pins_a>; |
|||
disable-wp; |
|||
st,neg-edge; |
|||
bus-width = <4>; |
|||
vmmc-supply = <&vdd_sd>; |
|||
status = "okay"; |
|||
}; |
|||
|
|||
&uart4 { |
|||
pinctrl-names = "default"; |
|||
pinctrl-0 = <&uart4_pins_a>; |
|||
status = "okay"; |
|||
}; |
|||
|
|||
&uart8 { |
|||
pinctrl-names = "default"; |
|||
pinctrl-0 = <&uart8_pins_a>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
&usart1 { |
|||
pinctrl-names = "default"; |
|||
pinctrl-0 = <&usart1_pins_a>; |
|||
uart-has-rtscts; |
|||
status = "disabled"; |
|||
}; |
|||
@ -0,0 +1,5 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
@ -0,0 +1,36 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#include "stm32mp13xa.dtsi" |
|||
|
|||
/ { |
|||
soc { |
|||
cryp: crypto@54002000 { |
|||
compatible = "st,stm32mp1-cryp"; |
|||
reg = <0x54002000 0x400>; |
|||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc CRYP1>; |
|||
resets = <&rcc CRYP1_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
saes: saes@54005000 { |
|||
compatible = "st,stm32-saes"; |
|||
reg = <0x54005000 0x400>; |
|||
clocks = <&rcc SAES_K>; |
|||
resets = <&rcc SAES_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
pka: pka@54006000 { |
|||
compatible = "st,stm32-pka64"; |
|||
reg = <0x54006000 0x2000>; |
|||
clocks = <&rcc PKA>; |
|||
resets = <&rcc PKA_R>; |
|||
status = "disabled"; |
|||
}; |
|||
}; |
|||
}; |
|||
@ -0,0 +1,5 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
@ -0,0 +1,35 @@ |
|||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
|||
/* |
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. |
|||
*/ |
|||
#include "stm32mp13xd.dtsi" |
|||
|
|||
/ { |
|||
soc { |
|||
cryp: crypto@54002000 { |
|||
compatible = "st,stm32mp1-cryp"; |
|||
reg = <0x54002000 0x400>; |
|||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
|||
clocks = <&rcc CRYP1>; |
|||
resets = <&rcc CRYP1_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
saes: saes@54005000 { |
|||
compatible = "st,stm32-saes"; |
|||
reg = <0x54005000 0x400>; |
|||
clocks = <&rcc SAES_K>; |
|||
resets = <&rcc SAES_R>; |
|||
status = "disabled"; |
|||
}; |
|||
|
|||
pka: pka@54006000 { |
|||
compatible = "st,stm32-pka64"; |
|||
reg = <0x54006000 0x2000>; |
|||
clocks = <&rcc PKA>; |
|||
resets = <&rcc PKA_R>; |
|||
status = "disabled"; |
|||
}; |
|||
}; |
|||
}; |
|||
File diff suppressed because it is too large
File diff suppressed because it is too large
File diff suppressed because it is too large
@ -1,278 +1,12 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved |
|||
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ |
|||
#define _DT_BINDINGS_STM32MP1_CLKS_H_ |
|||
|
|||
/* OSCILLATOR clocks */ |
|||
#define CK_HSE 0 |
|||
#define CK_CSI 1 |
|||
#define CK_LSI 2 |
|||
#define CK_LSE 3 |
|||
#define CK_HSI 4 |
|||
#define CK_HSE_DIV2 5 |
|||
|
|||
/* Bus clocks */ |
|||
#define TIM2 6 |
|||
#define TIM3 7 |
|||
#define TIM4 8 |
|||
#define TIM5 9 |
|||
#define TIM6 10 |
|||
#define TIM7 11 |
|||
#define TIM12 12 |
|||
#define TIM13 13 |
|||
#define TIM14 14 |
|||
#define LPTIM1 15 |
|||
#define SPI2 16 |
|||
#define SPI3 17 |
|||
#define USART2 18 |
|||
#define USART3 19 |
|||
#define UART4 20 |
|||
#define UART5 21 |
|||
#define UART7 22 |
|||
#define UART8 23 |
|||
#define I2C1 24 |
|||
#define I2C2 25 |
|||
#define I2C3 26 |
|||
#define I2C5 27 |
|||
#define SPDIF 28 |
|||
#define CEC 29 |
|||
#define DAC12 30 |
|||
#define MDIO 31 |
|||
#define TIM1 32 |
|||
#define TIM8 33 |
|||
#define TIM15 34 |
|||
#define TIM16 35 |
|||
#define TIM17 36 |
|||
#define SPI1 37 |
|||
#define SPI4 38 |
|||
#define SPI5 39 |
|||
#define USART6 40 |
|||
#define SAI1 41 |
|||
#define SAI2 42 |
|||
#define SAI3 43 |
|||
#define DFSDM 44 |
|||
#define FDCAN 45 |
|||
#define LPTIM2 46 |
|||
#define LPTIM3 47 |
|||
#define LPTIM4 48 |
|||
#define LPTIM5 49 |
|||
#define SAI4 50 |
|||
#define SYSCFG 51 |
|||
#define VREF 52 |
|||
#define TMPSENS 53 |
|||
#define PMBCTRL 54 |
|||
#define HDP 55 |
|||
#define LTDC 56 |
|||
#define DSI 57 |
|||
#define IWDG2 58 |
|||
#define USBPHY 59 |
|||
#define STGENRO 60 |
|||
#define SPI6 61 |
|||
#define I2C4 62 |
|||
#define I2C6 63 |
|||
#define USART1 64 |
|||
#define RTCAPB 65 |
|||
#define TZC1 66 |
|||
#define TZPC 67 |
|||
#define IWDG1 68 |
|||
#define BSEC 69 |
|||
#define STGEN 70 |
|||
#define DMA1 71 |
|||
#define DMA2 72 |
|||
#define DMAMUX 73 |
|||
#define ADC12 74 |
|||
#define USBO 75 |
|||
#define SDMMC3 76 |
|||
#define DCMI 77 |
|||
#define CRYP2 78 |
|||
#define HASH2 79 |
|||
#define RNG2 80 |
|||
#define CRC2 81 |
|||
#define HSEM 82 |
|||
#define IPCC 83 |
|||
#define GPIOA 84 |
|||
#define GPIOB 85 |
|||
#define GPIOC 86 |
|||
#define GPIOD 87 |
|||
#define GPIOE 88 |
|||
#define GPIOF 89 |
|||
#define GPIOG 90 |
|||
#define GPIOH 91 |
|||
#define GPIOI 92 |
|||
#define GPIOJ 93 |
|||
#define GPIOK 94 |
|||
#define GPIOZ 95 |
|||
#define CRYP1 96 |
|||
#define HASH1 97 |
|||
#define RNG1 98 |
|||
#define BKPSRAM 99 |
|||
#define MDMA 100 |
|||
#define GPU 101 |
|||
#define ETHCK 102 |
|||
#define ETHTX 103 |
|||
#define ETHRX 104 |
|||
#define ETHMAC 105 |
|||
#define FMC 106 |
|||
#define QSPI 107 |
|||
#define SDMMC1 108 |
|||
#define SDMMC2 109 |
|||
#define CRC1 110 |
|||
#define USBH 111 |
|||
#define ETHSTP 112 |
|||
#define TZC2 113 |
|||
|
|||
/* Kernel clocks */ |
|||
#define SDMMC1_K 118 |
|||
#define SDMMC2_K 119 |
|||
#define SDMMC3_K 120 |
|||
#define FMC_K 121 |
|||
#define QSPI_K 122 |
|||
#define ETHCK_K 123 |
|||
#define RNG1_K 124 |
|||
#define RNG2_K 125 |
|||
#define GPU_K 126 |
|||
#define USBPHY_K 127 |
|||
#define STGEN_K 128 |
|||
#define SPDIF_K 129 |
|||
#define SPI1_K 130 |
|||
#define SPI2_K 131 |
|||
#define SPI3_K 132 |
|||
#define SPI4_K 133 |
|||
#define SPI5_K 134 |
|||
#define SPI6_K 135 |
|||
#define CEC_K 136 |
|||
#define I2C1_K 137 |
|||
#define I2C2_K 138 |
|||
#define I2C3_K 139 |
|||
#define I2C4_K 140 |
|||
#define I2C5_K 141 |
|||
#define I2C6_K 142 |
|||
#define LPTIM1_K 143 |
|||
#define LPTIM2_K 144 |
|||
#define LPTIM3_K 145 |
|||
#define LPTIM4_K 146 |
|||
#define LPTIM5_K 147 |
|||
#define USART1_K 148 |
|||
#define USART2_K 149 |
|||
#define USART3_K 150 |
|||
#define UART4_K 151 |
|||
#define UART5_K 152 |
|||
#define USART6_K 153 |
|||
#define UART7_K 154 |
|||
#define UART8_K 155 |
|||
#define DFSDM_K 156 |
|||
#define FDCAN_K 157 |
|||
#define SAI1_K 158 |
|||
#define SAI2_K 159 |
|||
#define SAI3_K 160 |
|||
#define SAI4_K 161 |
|||
#define ADC12_K 162 |
|||
#define DSI_K 163 |
|||
#define DSI_PX 164 |
|||
#define ADFSDM_K 165 |
|||
#define USBO_K 166 |
|||
#define LTDC_PX 167 |
|||
#define DAC12_K 168 |
|||
#define ETHPTP_K 169 |
|||
|
|||
/* PLL */ |
|||
#define PLL1 176 |
|||
#define PLL2 177 |
|||
#define PLL3 178 |
|||
#define PLL4 179 |
|||
|
|||
/* ODF */ |
|||
#define PLL1_P 180 |
|||
#define PLL1_Q 181 |
|||
#define PLL1_R 182 |
|||
#define PLL2_P 183 |
|||
#define PLL2_Q 184 |
|||
#define PLL2_R 185 |
|||
#define PLL3_P 186 |
|||
#define PLL3_Q 187 |
|||
#define PLL3_R 188 |
|||
#define PLL4_P 189 |
|||
#define PLL4_Q 190 |
|||
#define PLL4_R 191 |
|||
|
|||
/* AUX */ |
|||
#define RTC 192 |
|||
|
|||
/* MCLK */ |
|||
#define CK_PER 193 |
|||
#define CK_MPU 194 |
|||
#define CK_AXI 195 |
|||
#define CK_MCU 196 |
|||
|
|||
/* Time base */ |
|||
#define TIM2_K 197 |
|||
#define TIM3_K 198 |
|||
#define TIM4_K 199 |
|||
#define TIM5_K 200 |
|||
#define TIM6_K 201 |
|||
#define TIM7_K 202 |
|||
#define TIM12_K 203 |
|||
#define TIM13_K 204 |
|||
#define TIM14_K 205 |
|||
#define TIM1_K 206 |
|||
#define TIM8_K 207 |
|||
#define TIM15_K 208 |
|||
#define TIM16_K 209 |
|||
#define TIM17_K 210 |
|||
|
|||
/* MCO clocks */ |
|||
#define CK_MCO1 211 |
|||
#define CK_MCO2 212 |
|||
|
|||
/* TRACE & DEBUG clocks */ |
|||
#define CK_DBG 214 |
|||
#define CK_TRACE 215 |
|||
|
|||
/* DDR */ |
|||
#define DDRC1 220 |
|||
#define DDRC1LP 221 |
|||
#define DDRC2 222 |
|||
#define DDRC2LP 223 |
|||
#define DDRPHYC 224 |
|||
#define DDRPHYCLP 225 |
|||
#define DDRCAPB 226 |
|||
#define DDRCAPBLP 227 |
|||
#define AXIDCG 228 |
|||
#define DDRPHYCAPB 229 |
|||
#define DDRPHYCAPBLP 230 |
|||
#define DDRPERFM 231 |
|||
|
|||
#define STM32MP1_LAST_CLK 232 |
|||
|
|||
/* SCMI clock identifiers */ |
|||
#define CK_SCMI0_HSE 0 |
|||
#define CK_SCMI0_HSI 1 |
|||
#define CK_SCMI0_CSI 2 |
|||
#define CK_SCMI0_LSE 3 |
|||
#define CK_SCMI0_LSI 4 |
|||
#define CK_SCMI0_PLL2_Q 5 |
|||
#define CK_SCMI0_PLL2_R 6 |
|||
#define CK_SCMI0_MPU 7 |
|||
#define CK_SCMI0_AXI 8 |
|||
#define CK_SCMI0_BSEC 9 |
|||
#define CK_SCMI0_CRYP1 10 |
|||
#define CK_SCMI0_GPIOZ 11 |
|||
#define CK_SCMI0_HASH1 12 |
|||
#define CK_SCMI0_I2C4 13 |
|||
#define CK_SCMI0_I2C6 14 |
|||
#define CK_SCMI0_IWDG1 15 |
|||
#define CK_SCMI0_RNG1 16 |
|||
#define CK_SCMI0_RTC 17 |
|||
#define CK_SCMI0_RTCAPB 18 |
|||
#define CK_SCMI0_SPI6 19 |
|||
#define CK_SCMI0_USART1 20 |
|||
|
|||
#define CK_SCMI1_PLL3_Q 0 |
|||
#define CK_SCMI1_PLL3_R 1 |
|||
#define CK_SCMI1_MCU 2 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ |
|||
#if STM32MP13 |
|||
#include "stm32mp13-clks.h" |
|||
#endif |
|||
#if STM32MP15 |
|||
#include "stm32mp15-clks.h" |
|||
#endif |
|||
|
|||
@ -1,283 +1,11 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved |
|||
* Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ |
|||
#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_ |
|||
|
|||
/* PLL output is enable when x=1, with x=p,q or r */ |
|||
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) |
|||
|
|||
/* st,clksrc: mandatory clock source */ |
|||
|
|||
#define CLK_MPU_HSI 0x00000200 |
|||
#define CLK_MPU_HSE 0x00000201 |
|||
#define CLK_MPU_PLL1P 0x00000202 |
|||
#define CLK_MPU_PLL1P_DIV 0x00000203 |
|||
|
|||
#define CLK_AXI_HSI 0x00000240 |
|||
#define CLK_AXI_HSE 0x00000241 |
|||
#define CLK_AXI_PLL2P 0x00000242 |
|||
|
|||
#define CLK_MCU_HSI 0x00000480 |
|||
#define CLK_MCU_HSE 0x00000481 |
|||
#define CLK_MCU_CSI 0x00000482 |
|||
#define CLK_MCU_PLL3P 0x00000483 |
|||
|
|||
#define CLK_PLL12_HSI 0x00000280 |
|||
#define CLK_PLL12_HSE 0x00000281 |
|||
|
|||
#define CLK_PLL3_HSI 0x00008200 |
|||
#define CLK_PLL3_HSE 0x00008201 |
|||
#define CLK_PLL3_CSI 0x00008202 |
|||
|
|||
#define CLK_PLL4_HSI 0x00008240 |
|||
#define CLK_PLL4_HSE 0x00008241 |
|||
#define CLK_PLL4_CSI 0x00008242 |
|||
#define CLK_PLL4_I2SCKIN 0x00008243 |
|||
|
|||
#define CLK_RTC_DISABLED 0x00001400 |
|||
#define CLK_RTC_LSE 0x00001401 |
|||
#define CLK_RTC_LSI 0x00001402 |
|||
#define CLK_RTC_HSE 0x00001403 |
|||
|
|||
#define CLK_MCO1_HSI 0x00008000 |
|||
#define CLK_MCO1_HSE 0x00008001 |
|||
#define CLK_MCO1_CSI 0x00008002 |
|||
#define CLK_MCO1_LSI 0x00008003 |
|||
#define CLK_MCO1_LSE 0x00008004 |
|||
#define CLK_MCO1_DISABLED 0x0000800F |
|||
|
|||
#define CLK_MCO2_MPU 0x00008040 |
|||
#define CLK_MCO2_AXI 0x00008041 |
|||
#define CLK_MCO2_MCU 0x00008042 |
|||
#define CLK_MCO2_PLL4P 0x00008043 |
|||
#define CLK_MCO2_HSE 0x00008044 |
|||
#define CLK_MCO2_HSI 0x00008045 |
|||
#define CLK_MCO2_DISABLED 0x0000804F |
|||
|
|||
/* st,pkcs: peripheral kernel clock source */ |
|||
|
|||
#define CLK_I2C12_PCLK1 0x00008C00 |
|||
#define CLK_I2C12_PLL4R 0x00008C01 |
|||
#define CLK_I2C12_HSI 0x00008C02 |
|||
#define CLK_I2C12_CSI 0x00008C03 |
|||
#define CLK_I2C12_DISABLED 0x00008C07 |
|||
|
|||
#define CLK_I2C35_PCLK1 0x00008C40 |
|||
#define CLK_I2C35_PLL4R 0x00008C41 |
|||
#define CLK_I2C35_HSI 0x00008C42 |
|||
#define CLK_I2C35_CSI 0x00008C43 |
|||
#define CLK_I2C35_DISABLED 0x00008C47 |
|||
|
|||
#define CLK_I2C46_PCLK5 0x00000C00 |
|||
#define CLK_I2C46_PLL3Q 0x00000C01 |
|||
#define CLK_I2C46_HSI 0x00000C02 |
|||
#define CLK_I2C46_CSI 0x00000C03 |
|||
#define CLK_I2C46_DISABLED 0x00000C07 |
|||
|
|||
#define CLK_SAI1_PLL4Q 0x00008C80 |
|||
#define CLK_SAI1_PLL3Q 0x00008C81 |
|||
#define CLK_SAI1_I2SCKIN 0x00008C82 |
|||
#define CLK_SAI1_CKPER 0x00008C83 |
|||
#define CLK_SAI1_PLL3R 0x00008C84 |
|||
#define CLK_SAI1_DISABLED 0x00008C87 |
|||
|
|||
#define CLK_SAI2_PLL4Q 0x00008CC0 |
|||
#define CLK_SAI2_PLL3Q 0x00008CC1 |
|||
#define CLK_SAI2_I2SCKIN 0x00008CC2 |
|||
#define CLK_SAI2_CKPER 0x00008CC3 |
|||
#define CLK_SAI2_SPDIF 0x00008CC4 |
|||
#define CLK_SAI2_PLL3R 0x00008CC5 |
|||
#define CLK_SAI2_DISABLED 0x00008CC7 |
|||
|
|||
#define CLK_SAI3_PLL4Q 0x00008D00 |
|||
#define CLK_SAI3_PLL3Q 0x00008D01 |
|||
#define CLK_SAI3_I2SCKIN 0x00008D02 |
|||
#define CLK_SAI3_CKPER 0x00008D03 |
|||
#define CLK_SAI3_PLL3R 0x00008D04 |
|||
#define CLK_SAI3_DISABLED 0x00008D07 |
|||
|
|||
#define CLK_SAI4_PLL4Q 0x00008D40 |
|||
#define CLK_SAI4_PLL3Q 0x00008D41 |
|||
#define CLK_SAI4_I2SCKIN 0x00008D42 |
|||
#define CLK_SAI4_CKPER 0x00008D43 |
|||
#define CLK_SAI4_PLL3R 0x00008D44 |
|||
#define CLK_SAI4_DISABLED 0x00008D47 |
|||
|
|||
#define CLK_SPI2S1_PLL4P 0x00008D80 |
|||
#define CLK_SPI2S1_PLL3Q 0x00008D81 |
|||
#define CLK_SPI2S1_I2SCKIN 0x00008D82 |
|||
#define CLK_SPI2S1_CKPER 0x00008D83 |
|||
#define CLK_SPI2S1_PLL3R 0x00008D84 |
|||
#define CLK_SPI2S1_DISABLED 0x00008D87 |
|||
|
|||
#define CLK_SPI2S23_PLL4P 0x00008DC0 |
|||
#define CLK_SPI2S23_PLL3Q 0x00008DC1 |
|||
#define CLK_SPI2S23_I2SCKIN 0x00008DC2 |
|||
#define CLK_SPI2S23_CKPER 0x00008DC3 |
|||
#define CLK_SPI2S23_PLL3R 0x00008DC4 |
|||
#define CLK_SPI2S23_DISABLED 0x00008DC7 |
|||
|
|||
#define CLK_SPI45_PCLK2 0x00008E00 |
|||
#define CLK_SPI45_PLL4Q 0x00008E01 |
|||
#define CLK_SPI45_HSI 0x00008E02 |
|||
#define CLK_SPI45_CSI 0x00008E03 |
|||
#define CLK_SPI45_HSE 0x00008E04 |
|||
#define CLK_SPI45_DISABLED 0x00008E07 |
|||
|
|||
#define CLK_SPI6_PCLK5 0x00000C40 |
|||
#define CLK_SPI6_PLL4Q 0x00000C41 |
|||
#define CLK_SPI6_HSI 0x00000C42 |
|||
#define CLK_SPI6_CSI 0x00000C43 |
|||
#define CLK_SPI6_HSE 0x00000C44 |
|||
#define CLK_SPI6_PLL3Q 0x00000C45 |
|||
#define CLK_SPI6_DISABLED 0x00000C47 |
|||
|
|||
#define CLK_UART6_PCLK2 0x00008E40 |
|||
#define CLK_UART6_PLL4Q 0x00008E41 |
|||
#define CLK_UART6_HSI 0x00008E42 |
|||
#define CLK_UART6_CSI 0x00008E43 |
|||
#define CLK_UART6_HSE 0x00008E44 |
|||
#define CLK_UART6_DISABLED 0x00008E47 |
|||
|
|||
#define CLK_UART24_PCLK1 0x00008E80 |
|||
#define CLK_UART24_PLL4Q 0x00008E81 |
|||
#define CLK_UART24_HSI 0x00008E82 |
|||
#define CLK_UART24_CSI 0x00008E83 |
|||
#define CLK_UART24_HSE 0x00008E84 |
|||
#define CLK_UART24_DISABLED 0x00008E87 |
|||
|
|||
#define CLK_UART35_PCLK1 0x00008EC0 |
|||
#define CLK_UART35_PLL4Q 0x00008EC1 |
|||
#define CLK_UART35_HSI 0x00008EC2 |
|||
#define CLK_UART35_CSI 0x00008EC3 |
|||
#define CLK_UART35_HSE 0x00008EC4 |
|||
#define CLK_UART35_DISABLED 0x00008EC7 |
|||
|
|||
#define CLK_UART78_PCLK1 0x00008F00 |
|||
#define CLK_UART78_PLL4Q 0x00008F01 |
|||
#define CLK_UART78_HSI 0x00008F02 |
|||
#define CLK_UART78_CSI 0x00008F03 |
|||
#define CLK_UART78_HSE 0x00008F04 |
|||
#define CLK_UART78_DISABLED 0x00008F07 |
|||
|
|||
#define CLK_UART1_PCLK5 0x00000C80 |
|||
#define CLK_UART1_PLL3Q 0x00000C81 |
|||
#define CLK_UART1_HSI 0x00000C82 |
|||
#define CLK_UART1_CSI 0x00000C83 |
|||
#define CLK_UART1_PLL4Q 0x00000C84 |
|||
#define CLK_UART1_HSE 0x00000C85 |
|||
#define CLK_UART1_DISABLED 0x00000C87 |
|||
|
|||
#define CLK_SDMMC12_HCLK6 0x00008F40 |
|||
#define CLK_SDMMC12_PLL3R 0x00008F41 |
|||
#define CLK_SDMMC12_PLL4P 0x00008F42 |
|||
#define CLK_SDMMC12_HSI 0x00008F43 |
|||
#define CLK_SDMMC12_DISABLED 0x00008F47 |
|||
|
|||
#define CLK_SDMMC3_HCLK2 0x00008F80 |
|||
#define CLK_SDMMC3_PLL3R 0x00008F81 |
|||
#define CLK_SDMMC3_PLL4P 0x00008F82 |
|||
#define CLK_SDMMC3_HSI 0x00008F83 |
|||
#define CLK_SDMMC3_DISABLED 0x00008F87 |
|||
|
|||
#define CLK_ETH_PLL4P 0x00008FC0 |
|||
#define CLK_ETH_PLL3Q 0x00008FC1 |
|||
#define CLK_ETH_DISABLED 0x00008FC3 |
|||
|
|||
#define CLK_QSPI_ACLK 0x00009000 |
|||
#define CLK_QSPI_PLL3R 0x00009001 |
|||
#define CLK_QSPI_PLL4P 0x00009002 |
|||
#define CLK_QSPI_CKPER 0x00009003 |
|||
|
|||
#define CLK_FMC_ACLK 0x00009040 |
|||
#define CLK_FMC_PLL3R 0x00009041 |
|||
#define CLK_FMC_PLL4P 0x00009042 |
|||
#define CLK_FMC_CKPER 0x00009043 |
|||
|
|||
#define CLK_FDCAN_HSE 0x000090C0 |
|||
#define CLK_FDCAN_PLL3Q 0x000090C1 |
|||
#define CLK_FDCAN_PLL4Q 0x000090C2 |
|||
#define CLK_FDCAN_PLL4R 0x000090C3 |
|||
|
|||
#define CLK_SPDIF_PLL4P 0x00009140 |
|||
#define CLK_SPDIF_PLL3Q 0x00009141 |
|||
#define CLK_SPDIF_HSI 0x00009142 |
|||
#define CLK_SPDIF_DISABLED 0x00009143 |
|||
|
|||
#define CLK_CEC_LSE 0x00009180 |
|||
#define CLK_CEC_LSI 0x00009181 |
|||
#define CLK_CEC_CSI_DIV122 0x00009182 |
|||
#define CLK_CEC_DISABLED 0x00009183 |
|||
|
|||
#define CLK_USBPHY_HSE 0x000091C0 |
|||
#define CLK_USBPHY_PLL4R 0x000091C1 |
|||
#define CLK_USBPHY_HSE_DIV2 0x000091C2 |
|||
#define CLK_USBPHY_DISABLED 0x000091C3 |
|||
|
|||
#define CLK_USBO_PLL4R 0x800091C0 |
|||
#define CLK_USBO_USBPHY 0x800091C1 |
|||
|
|||
#define CLK_RNG1_CSI 0x00000CC0 |
|||
#define CLK_RNG1_PLL4R 0x00000CC1 |
|||
#define CLK_RNG1_LSE 0x00000CC2 |
|||
#define CLK_RNG1_LSI 0x00000CC3 |
|||
|
|||
#define CLK_RNG2_CSI 0x00009200 |
|||
#define CLK_RNG2_PLL4R 0x00009201 |
|||
#define CLK_RNG2_LSE 0x00009202 |
|||
#define CLK_RNG2_LSI 0x00009203 |
|||
|
|||
#define CLK_CKPER_HSI 0x00000D00 |
|||
#define CLK_CKPER_CSI 0x00000D01 |
|||
#define CLK_CKPER_HSE 0x00000D02 |
|||
#define CLK_CKPER_DISABLED 0x00000D03 |
|||
|
|||
#define CLK_STGEN_HSI 0x00000D40 |
|||
#define CLK_STGEN_HSE 0x00000D41 |
|||
#define CLK_STGEN_DISABLED 0x00000D43 |
|||
|
|||
#define CLK_DSI_DSIPLL 0x00009240 |
|||
#define CLK_DSI_PLL4P 0x00009241 |
|||
|
|||
#define CLK_ADC_PLL4R 0x00009280 |
|||
#define CLK_ADC_CKPER 0x00009281 |
|||
#define CLK_ADC_PLL3Q 0x00009282 |
|||
#define CLK_ADC_DISABLED 0x00009283 |
|||
|
|||
#define CLK_LPTIM45_PCLK3 0x000092C0 |
|||
#define CLK_LPTIM45_PLL4P 0x000092C1 |
|||
#define CLK_LPTIM45_PLL3Q 0x000092C2 |
|||
#define CLK_LPTIM45_LSE 0x000092C3 |
|||
#define CLK_LPTIM45_LSI 0x000092C4 |
|||
#define CLK_LPTIM45_CKPER 0x000092C5 |
|||
#define CLK_LPTIM45_DISABLED 0x000092C7 |
|||
|
|||
#define CLK_LPTIM23_PCLK3 0x00009300 |
|||
#define CLK_LPTIM23_PLL4Q 0x00009301 |
|||
#define CLK_LPTIM23_CKPER 0x00009302 |
|||
#define CLK_LPTIM23_LSE 0x00009303 |
|||
#define CLK_LPTIM23_LSI 0x00009304 |
|||
#define CLK_LPTIM23_DISABLED 0x00009307 |
|||
|
|||
#define CLK_LPTIM1_PCLK1 0x00009340 |
|||
#define CLK_LPTIM1_PLL4P 0x00009341 |
|||
#define CLK_LPTIM1_PLL3Q 0x00009342 |
|||
#define CLK_LPTIM1_LSE 0x00009343 |
|||
#define CLK_LPTIM1_LSI 0x00009344 |
|||
#define CLK_LPTIM1_CKPER 0x00009345 |
|||
#define CLK_LPTIM1_DISABLED 0x00009347 |
|||
|
|||
/* define for st,pll /csg */ |
|||
#define SSCG_MODE_CENTER_SPREAD 0 |
|||
#define SSCG_MODE_DOWN_SPREAD 1 |
|||
|
|||
/* define for st,drive */ |
|||
#define LSEDRV_LOWEST 0 |
|||
#define LSEDRV_MEDIUM_LOW 1 |
|||
#define LSEDRV_MEDIUM_HIGH 2 |
|||
#define LSEDRV_HIGHEST 3 |
|||
|
|||
#if STM32MP13 |
|||
#include "stm32mp13-clksrc.h" |
|||
#endif |
|||
#if STM32MP15 |
|||
#include "stm32mp15-clksrc.h" |
|||
#endif |
|||
|
|||
@ -0,0 +1,230 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP13_CLKS_H_ |
|||
#define _DT_BINDINGS_STM32MP13_CLKS_H_ |
|||
|
|||
/* OSCILLATOR clocks */ |
|||
#define CK_HSE 0 |
|||
#define CK_CSI 1 |
|||
#define CK_LSI 2 |
|||
#define CK_LSE 3 |
|||
#define CK_HSI 4 |
|||
#define CK_HSE_DIV2 5 |
|||
|
|||
/* PLL */ |
|||
#define PLL1 6 |
|||
#define PLL2 7 |
|||
#define PLL3 8 |
|||
#define PLL4 9 |
|||
|
|||
/* ODF */ |
|||
#define PLL1_P 10 |
|||
#define PLL1_Q 11 |
|||
#define PLL1_R 12 |
|||
#define PLL2_P 13 |
|||
#define PLL2_Q 14 |
|||
#define PLL2_R 15 |
|||
#define PLL3_P 16 |
|||
#define PLL3_Q 17 |
|||
#define PLL3_R 18 |
|||
#define PLL4_P 19 |
|||
#define PLL4_Q 20 |
|||
#define PLL4_R 21 |
|||
|
|||
#define PCLK1 22 |
|||
#define PCLK2 23 |
|||
#define PCLK3 24 |
|||
#define PCLK4 25 |
|||
#define PCLK5 26 |
|||
#define PCLK6 27 |
|||
|
|||
/* SYSTEM CLOCK */ |
|||
#define CK_PER 28 |
|||
#define CK_MPU 29 |
|||
#define CK_AXI 30 |
|||
#define CK_MLAHB 31 |
|||
|
|||
/* BASE TIMER */ |
|||
#define CK_TIMG1 32 |
|||
#define CK_TIMG2 33 |
|||
#define CK_TIMG3 34 |
|||
|
|||
/* AUX */ |
|||
#define RTC 35 |
|||
|
|||
/* TRACE & DEBUG clocks */ |
|||
#define CK_DBG 36 |
|||
#define CK_TRACE 37 |
|||
|
|||
/* MCO clocks */ |
|||
#define CK_MCO1 38 |
|||
#define CK_MCO2 39 |
|||
|
|||
/* IP clocks */ |
|||
#define SYSCFG 40 |
|||
#define VREF 41 |
|||
#define TMPSENS 42 |
|||
#define PMBCTRL 43 |
|||
#define HDP 44 |
|||
#define IWDG2 45 |
|||
#define STGENRO 46 |
|||
#define USART1 47 |
|||
#define RTCAPB 48 |
|||
#define TZC 49 |
|||
#define TZPC 50 |
|||
#define IWDG1 51 |
|||
#define BSEC 52 |
|||
#define DMA1 53 |
|||
#define DMA2 54 |
|||
#define DMAMUX1 55 |
|||
#define DMAMUX2 56 |
|||
#define GPIOA 57 |
|||
#define GPIOB 58 |
|||
#define GPIOC 59 |
|||
#define GPIOD 60 |
|||
#define GPIOE 61 |
|||
#define GPIOF 62 |
|||
#define GPIOG 63 |
|||
#define GPIOH 64 |
|||
#define GPIOI 65 |
|||
#define CRYP1 66 |
|||
#define HASH1 67 |
|||
#define BKPSRAM 68 |
|||
#define MDMA 69 |
|||
#define CRC1 70 |
|||
#define USBH 71 |
|||
#define DMA3 72 |
|||
#define TSC 73 |
|||
#define PKA 74 |
|||
#define AXIMC 75 |
|||
#define MCE 76 |
|||
#define ETH1TX 77 |
|||
#define ETH2TX 78 |
|||
#define ETH1RX 79 |
|||
#define ETH2RX 80 |
|||
#define ETH1MAC 81 |
|||
#define ETH2MAC 82 |
|||
#define ETH1STP 83 |
|||
#define ETH2STP 84 |
|||
|
|||
/* IP clocks with parents */ |
|||
#define SDMMC1_K 85 |
|||
#define SDMMC2_K 86 |
|||
#define ADC1_K 87 |
|||
#define ADC2_K 88 |
|||
#define FMC_K 89 |
|||
#define QSPI_K 90 |
|||
#define RNG1_K 91 |
|||
#define USBPHY_K 92 |
|||
#define STGEN_K 93 |
|||
#define SPDIF_K 94 |
|||
#define SPI1_K 95 |
|||
#define SPI2_K 96 |
|||
#define SPI3_K 97 |
|||
#define SPI4_K 98 |
|||
#define SPI5_K 99 |
|||
#define I2C1_K 100 |
|||
#define I2C2_K 101 |
|||
#define I2C3_K 102 |
|||
#define I2C4_K 103 |
|||
#define I2C5_K 104 |
|||
#define TIM2_K 105 |
|||
#define TIM3_K 106 |
|||
#define TIM4_K 107 |
|||
#define TIM5_K 108 |
|||
#define TIM6_K 109 |
|||
#define TIM7_K 110 |
|||
#define TIM12_K 111 |
|||
#define TIM13_K 112 |
|||
#define TIM14_K 113 |
|||
#define TIM1_K 114 |
|||
#define TIM8_K 115 |
|||
#define TIM15_K 116 |
|||
#define TIM16_K 117 |
|||
#define TIM17_K 118 |
|||
#define LPTIM1_K 119 |
|||
#define LPTIM2_K 120 |
|||
#define LPTIM3_K 121 |
|||
#define LPTIM4_K 122 |
|||
#define LPTIM5_K 123 |
|||
#define USART1_K 124 |
|||
#define USART2_K 125 |
|||
#define USART3_K 126 |
|||
#define UART4_K 127 |
|||
#define UART5_K 128 |
|||
#define USART6_K 129 |
|||
#define UART7_K 130 |
|||
#define UART8_K 131 |
|||
#define DFSDM_K 132 |
|||
#define FDCAN_K 133 |
|||
#define SAI1_K 134 |
|||
#define SAI2_K 135 |
|||
#define ADFSDM_K 136 |
|||
#define USBO_K 137 |
|||
#define LTDC_PX 138 |
|||
#define ETH1CK_K 139 |
|||
#define ETH1PTP_K 140 |
|||
#define ETH2CK_K 141 |
|||
#define ETH2PTP_K 142 |
|||
#define DCMIPP_K 143 |
|||
#define SAES_K 144 |
|||
#define DTS_K 145 |
|||
|
|||
/* DDR */ |
|||
#define DDRC1 146 |
|||
#define DDRC1LP 147 |
|||
#define DDRC2 148 |
|||
#define DDRC2LP 149 |
|||
#define DDRPHYC 150 |
|||
#define DDRPHYCLP 151 |
|||
#define DDRCAPB 152 |
|||
#define DDRCAPBLP 153 |
|||
#define AXIDCG 154 |
|||
#define DDRPHYCAPB 155 |
|||
#define DDRPHYCAPBLP 156 |
|||
#define DDRPERFM 157 |
|||
|
|||
#define ADC1 158 |
|||
#define ADC2 159 |
|||
#define SAI1 160 |
|||
#define SAI2 161 |
|||
|
|||
#define STM32MP1_LAST_CLK 162 |
|||
|
|||
/* SCMI clock identifiers */ |
|||
#define CK_SCMI0_HSE 0 |
|||
#define CK_SCMI0_HSI 1 |
|||
#define CK_SCMI0_CSI 2 |
|||
#define CK_SCMI0_LSE 3 |
|||
#define CK_SCMI0_LSI 4 |
|||
#define CK_SCMI0_HSE_DIV2 5 |
|||
#define CK_SCMI0_PLL2_Q 6 |
|||
#define CK_SCMI0_PLL2_R 7 |
|||
#define CK_SCMI0_PLL3_P 8 |
|||
#define CK_SCMI0_PLL3_Q 9 |
|||
#define CK_SCMI0_PLL3_R 10 |
|||
#define CK_SCMI0_PLL4_P 11 |
|||
#define CK_SCMI0_PLL4_Q 12 |
|||
#define CK_SCMI0_PLL4_R 13 |
|||
#define CK_SCMI0_MPU 14 |
|||
#define CK_SCMI0_AXI 15 |
|||
#define CK_SCMI0_MLAHB 16 |
|||
#define CK_SCMI0_CKPER 17 |
|||
#define CK_SCMI0_PCLK1 18 |
|||
#define CK_SCMI0_PCLK2 19 |
|||
#define CK_SCMI0_PCLK3 20 |
|||
#define CK_SCMI0_PCLK4 21 |
|||
#define CK_SCMI0_PCLK5 22 |
|||
#define CK_SCMI0_PCLK6 23 |
|||
#define CK_SCMI0_CKTIMG1 24 |
|||
#define CK_SCMI0_CKTIMG2 25 |
|||
#define CK_SCMI0_CKTIMG3 26 |
|||
#define CK_SCMI0_RTC 27 |
|||
#define CK_SCMI0_RTCAPB 28 |
|||
#define CK_SCMI0_BSEC 29 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP13_CLKS_H_ */ |
|||
@ -0,0 +1,394 @@ |
|||
/*
|
|||
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved |
|||
* |
|||
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ |
|||
#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ |
|||
|
|||
#define CMD_DIV 0 |
|||
#define CMD_MUX 1 |
|||
#define CMD_CLK 2 |
|||
#define CMD_RESERVED1 3 |
|||
|
|||
#define CMD_SHIFT 26 |
|||
#define CMD_MASK 0xFC000000 |
|||
#define CMD_DATA_MASK 0x03FFFFFF |
|||
|
|||
#define DIV_ID_SHIFT 8 |
|||
#define DIV_ID_MASK 0x0000FF00 |
|||
|
|||
#define DIV_DIVN_SHIFT 0 |
|||
#define DIV_DIVN_MASK 0x000000FF |
|||
|
|||
#define MUX_ID_SHIFT 4 |
|||
#define MUX_ID_MASK 0x00000FF0 |
|||
|
|||
#define MUX_SEL_SHIFT 0 |
|||
#define MUX_SEL_MASK 0x0000000F |
|||
|
|||
#define CLK_ID_MASK GENMASK_32(19, 11) |
|||
#define CLK_ID_SHIFT 11 |
|||
#define CLK_ON_MASK 0x00000400 |
|||
#define CLK_ON_SHIFT 10 |
|||
#define CLK_DIV_MASK GENMASK_32(9, 4) |
|||
#define CLK_DIV_SHIFT 4 |
|||
#define CLK_SEL_MASK GENMASK_32(3, 0) |
|||
#define CLK_SEL_SHIFT 0 |
|||
|
|||
#define DIV_PLL1DIVP 0 |
|||
#define DIV_PLL2DIVP 1 |
|||
#define DIV_PLL2DIVQ 2 |
|||
#define DIV_PLL2DIVR 3 |
|||
#define DIV_PLL3DIVP 4 |
|||
#define DIV_PLL3DIVQ 5 |
|||
#define DIV_PLL3DIVR 6 |
|||
#define DIV_PLL4DIVP 7 |
|||
#define DIV_PLL4DIVQ 8 |
|||
#define DIV_PLL4DIVR 9 |
|||
#define DIV_MPU 10 |
|||
#define DIV_AXI 11 |
|||
#define DIV_MLAHB 12 |
|||
#define DIV_APB1 13 |
|||
#define DIV_APB2 14 |
|||
#define DIV_APB3 15 |
|||
#define DIV_APB4 16 |
|||
#define DIV_APB5 17 |
|||
#define DIV_APB6 18 |
|||
#define DIV_RTC 19 |
|||
#define DIV_MCO1 20 |
|||
#define DIV_MCO2 21 |
|||
#define DIV_HSI 22 |
|||
#define DIV_TRACE 23 |
|||
#define DIV_ETH1PTP 24 |
|||
#define DIV_ETH2PTP 25 |
|||
#define DIV_MAX 26 |
|||
|
|||
#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ |
|||
((div_id) << DIV_ID_SHIFT |\ |
|||
(div))) |
|||
|
|||
#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ |
|||
((mux_id) << MUX_ID_SHIFT |\ |
|||
(sel))) |
|||
|
|||
/* MCO output is enable */ |
|||
#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ |
|||
(((mco_id) << CLK_ID_SHIFT) |\ |
|||
(sel)) | CLK_ON_MASK) |
|||
|
|||
#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ |
|||
((mco_id) << CLK_ID_SHIFT)) |
|||
|
|||
/* CLK output is enable */ |
|||
#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ |
|||
(((clk_id) << CLK_ID_SHIFT) |\ |
|||
(sel)) | CLK_ON_MASK) |
|||
|
|||
#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ |
|||
((clk_id) << CLK_ID_SHIFT)) |
|||
|
|||
#define MUX_MPU 0 |
|||
#define MUX_AXI 1 |
|||
#define MUX_MLAHB 2 |
|||
#define MUX_PLL12 3 |
|||
#define MUX_PLL3 4 |
|||
#define MUX_PLL4 5 |
|||
#define MUX_RTC 6 |
|||
#define MUX_MCO1 7 |
|||
#define MUX_MCO2 8 |
|||
#define MUX_CKPER 9 |
|||
#define MUX_KERNEL_BEGIN 10 |
|||
#define MUX_ADC1 10 |
|||
#define MUX_ADC2 11 |
|||
#define MUX_DCMIPP 12 |
|||
#define MUX_ETH1 13 |
|||
#define MUX_ETH2 14 |
|||
#define MUX_FDCAN 15 |
|||
#define MUX_FMC 16 |
|||
#define MUX_I2C12 17 |
|||
#define MUX_I2C3 18 |
|||
#define MUX_I2C4 19 |
|||
#define MUX_I2C5 20 |
|||
#define MUX_LPTIM1 21 |
|||
#define MUX_LPTIM2 22 |
|||
#define MUX_LPTIM3 23 |
|||
#define MUX_LPTIM45 24 |
|||
#define MUX_QSPI 25 |
|||
#define MUX_RNG1 26 |
|||
#define MUX_SAES 27 |
|||
#define MUX_SAI1 28 |
|||
#define MUX_SAI2 29 |
|||
#define MUX_SDMMC1 30 |
|||
#define MUX_SDMMC2 31 |
|||
#define MUX_SPDIF 32 |
|||
#define MUX_SPI1 33 |
|||
#define MUX_SPI23 34 |
|||
#define MUX_SPI4 35 |
|||
#define MUX_SPI5 36 |
|||
#define MUX_STGEN 37 |
|||
#define MUX_UART1 38 |
|||
#define MUX_UART2 39 |
|||
#define MUX_UART35 40 |
|||
#define MUX_UART4 41 |
|||
#define MUX_UART6 42 |
|||
#define MUX_UART78 43 |
|||
#define MUX_USBO 44 |
|||
#define MUX_USBPHY 45 |
|||
#define MUX_MAX 46 |
|||
|
|||
#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) |
|||
#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) |
|||
#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) |
|||
#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) |
|||
|
|||
#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) |
|||
#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) |
|||
#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) |
|||
|
|||
#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) |
|||
#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) |
|||
#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) |
|||
#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) |
|||
|
|||
#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) |
|||
#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) |
|||
|
|||
#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) |
|||
#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) |
|||
#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) |
|||
|
|||
#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) |
|||
#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) |
|||
#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) |
|||
|
|||
#define CLK_RTC_DISABLED CLK_DISABLED(RTC) |
|||
#define CLK_RTC_LSE CLK_SRC(RTC, 1) |
|||
#define CLK_RTC_LSI CLK_SRC(RTC, 2) |
|||
#define CLK_RTC_HSE CLK_SRC(RTC, 3) |
|||
|
|||
#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) |
|||
#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) |
|||
#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) |
|||
#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) |
|||
#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) |
|||
#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) |
|||
|
|||
#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) |
|||
#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) |
|||
#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) |
|||
#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) |
|||
#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) |
|||
#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) |
|||
#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) |
|||
|
|||
#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) |
|||
#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) |
|||
#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) |
|||
#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) |
|||
|
|||
#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) |
|||
#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) |
|||
#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) |
|||
#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) |
|||
|
|||
#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) |
|||
#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) |
|||
#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) |
|||
#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) |
|||
|
|||
#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) |
|||
#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) |
|||
#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) |
|||
#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) |
|||
|
|||
#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) |
|||
#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) |
|||
#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) |
|||
#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) |
|||
|
|||
#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) |
|||
#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) |
|||
#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) |
|||
#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) |
|||
#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) |
|||
|
|||
#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) |
|||
#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) |
|||
#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) |
|||
#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) |
|||
#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) |
|||
|
|||
#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) |
|||
#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) |
|||
#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) |
|||
#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) |
|||
#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) |
|||
#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) |
|||
|
|||
#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) |
|||
#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) |
|||
#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) |
|||
#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) |
|||
#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) |
|||
|
|||
#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) |
|||
#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) |
|||
#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) |
|||
#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) |
|||
#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) |
|||
#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) |
|||
|
|||
#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) |
|||
#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) |
|||
#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) |
|||
#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) |
|||
#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) |
|||
#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) |
|||
|
|||
#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) |
|||
#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) |
|||
#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) |
|||
#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) |
|||
#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) |
|||
|
|||
#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) |
|||
#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) |
|||
#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) |
|||
#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) |
|||
#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) |
|||
|
|||
#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) |
|||
#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) |
|||
#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) |
|||
#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) |
|||
#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) |
|||
|
|||
#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) |
|||
#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) |
|||
#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) |
|||
#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) |
|||
#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) |
|||
|
|||
#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) |
|||
#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) |
|||
#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) |
|||
#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) |
|||
#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) |
|||
#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) |
|||
|
|||
#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) |
|||
#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) |
|||
#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) |
|||
#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) |
|||
#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) |
|||
|
|||
#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) |
|||
#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) |
|||
#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) |
|||
#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) |
|||
#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) |
|||
|
|||
#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) |
|||
#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) |
|||
#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) |
|||
#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) |
|||
#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) |
|||
#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) |
|||
|
|||
#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) |
|||
#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) |
|||
#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) |
|||
#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) |
|||
#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) |
|||
|
|||
#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) |
|||
#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) |
|||
#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) |
|||
#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) |
|||
#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) |
|||
#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) |
|||
|
|||
#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) |
|||
#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) |
|||
#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) |
|||
#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) |
|||
|
|||
#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) |
|||
#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) |
|||
#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) |
|||
|
|||
#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) |
|||
#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) |
|||
#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) |
|||
|
|||
#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) |
|||
#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) |
|||
#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) |
|||
|
|||
#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) |
|||
#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) |
|||
#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) |
|||
#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) |
|||
|
|||
#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) |
|||
#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) |
|||
#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) |
|||
#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) |
|||
|
|||
#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) |
|||
#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) |
|||
|
|||
#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) |
|||
#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) |
|||
|
|||
#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) |
|||
#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) |
|||
#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) |
|||
|
|||
#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) |
|||
#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) |
|||
|
|||
#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) |
|||
#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) |
|||
#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) |
|||
#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) |
|||
|
|||
#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) |
|||
#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) |
|||
#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) |
|||
#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) |
|||
|
|||
#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) |
|||
#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) |
|||
/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ |
|||
#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) |
|||
|
|||
#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) |
|||
#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) |
|||
|
|||
#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) |
|||
#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) |
|||
#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) |
|||
#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) |
|||
|
|||
#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) |
|||
#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) |
|||
#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) |
|||
#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) |
|||
|
|||
/* PLL output is enable when x=1, with x=p,q or r */ |
|||
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) |
|||
|
|||
/* define for st,pll /csg */ |
|||
#define SSCG_MODE_CENTER_SPREAD 0 |
|||
#define SSCG_MODE_DOWN_SPREAD 1 |
|||
|
|||
/* define for st,drive */ |
|||
#define LSEDRV_LOWEST 0 |
|||
#define LSEDRV_MEDIUM_LOW 1 |
|||
#define LSEDRV_MEDIUM_HIGH 2 |
|||
#define LSEDRV_HIGHEST 3 |
|||
|
|||
#endif /* _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ */ |
|||
@ -0,0 +1,278 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ |
|||
#define _DT_BINDINGS_STM32MP1_CLKS_H_ |
|||
|
|||
/* OSCILLATOR clocks */ |
|||
#define CK_HSE 0 |
|||
#define CK_CSI 1 |
|||
#define CK_LSI 2 |
|||
#define CK_LSE 3 |
|||
#define CK_HSI 4 |
|||
#define CK_HSE_DIV2 5 |
|||
|
|||
/* Bus clocks */ |
|||
#define TIM2 6 |
|||
#define TIM3 7 |
|||
#define TIM4 8 |
|||
#define TIM5 9 |
|||
#define TIM6 10 |
|||
#define TIM7 11 |
|||
#define TIM12 12 |
|||
#define TIM13 13 |
|||
#define TIM14 14 |
|||
#define LPTIM1 15 |
|||
#define SPI2 16 |
|||
#define SPI3 17 |
|||
#define USART2 18 |
|||
#define USART3 19 |
|||
#define UART4 20 |
|||
#define UART5 21 |
|||
#define UART7 22 |
|||
#define UART8 23 |
|||
#define I2C1 24 |
|||
#define I2C2 25 |
|||
#define I2C3 26 |
|||
#define I2C5 27 |
|||
#define SPDIF 28 |
|||
#define CEC 29 |
|||
#define DAC12 30 |
|||
#define MDIO 31 |
|||
#define TIM1 32 |
|||
#define TIM8 33 |
|||
#define TIM15 34 |
|||
#define TIM16 35 |
|||
#define TIM17 36 |
|||
#define SPI1 37 |
|||
#define SPI4 38 |
|||
#define SPI5 39 |
|||
#define USART6 40 |
|||
#define SAI1 41 |
|||
#define SAI2 42 |
|||
#define SAI3 43 |
|||
#define DFSDM 44 |
|||
#define FDCAN 45 |
|||
#define LPTIM2 46 |
|||
#define LPTIM3 47 |
|||
#define LPTIM4 48 |
|||
#define LPTIM5 49 |
|||
#define SAI4 50 |
|||
#define SYSCFG 51 |
|||
#define VREF 52 |
|||
#define TMPSENS 53 |
|||
#define PMBCTRL 54 |
|||
#define HDP 55 |
|||
#define LTDC 56 |
|||
#define DSI 57 |
|||
#define IWDG2 58 |
|||
#define USBPHY 59 |
|||
#define STGENRO 60 |
|||
#define SPI6 61 |
|||
#define I2C4 62 |
|||
#define I2C6 63 |
|||
#define USART1 64 |
|||
#define RTCAPB 65 |
|||
#define TZC1 66 |
|||
#define TZPC 67 |
|||
#define IWDG1 68 |
|||
#define BSEC 69 |
|||
#define STGEN 70 |
|||
#define DMA1 71 |
|||
#define DMA2 72 |
|||
#define DMAMUX 73 |
|||
#define ADC12 74 |
|||
#define USBO 75 |
|||
#define SDMMC3 76 |
|||
#define DCMI 77 |
|||
#define CRYP2 78 |
|||
#define HASH2 79 |
|||
#define RNG2 80 |
|||
#define CRC2 81 |
|||
#define HSEM 82 |
|||
#define IPCC 83 |
|||
#define GPIOA 84 |
|||
#define GPIOB 85 |
|||
#define GPIOC 86 |
|||
#define GPIOD 87 |
|||
#define GPIOE 88 |
|||
#define GPIOF 89 |
|||
#define GPIOG 90 |
|||
#define GPIOH 91 |
|||
#define GPIOI 92 |
|||
#define GPIOJ 93 |
|||
#define GPIOK 94 |
|||
#define GPIOZ 95 |
|||
#define CRYP1 96 |
|||
#define HASH1 97 |
|||
#define RNG1 98 |
|||
#define BKPSRAM 99 |
|||
#define MDMA 100 |
|||
#define GPU 101 |
|||
#define ETHCK 102 |
|||
#define ETHTX 103 |
|||
#define ETHRX 104 |
|||
#define ETHMAC 105 |
|||
#define FMC 106 |
|||
#define QSPI 107 |
|||
#define SDMMC1 108 |
|||
#define SDMMC2 109 |
|||
#define CRC1 110 |
|||
#define USBH 111 |
|||
#define ETHSTP 112 |
|||
#define TZC2 113 |
|||
|
|||
/* Kernel clocks */ |
|||
#define SDMMC1_K 118 |
|||
#define SDMMC2_K 119 |
|||
#define SDMMC3_K 120 |
|||
#define FMC_K 121 |
|||
#define QSPI_K 122 |
|||
#define ETHCK_K 123 |
|||
#define RNG1_K 124 |
|||
#define RNG2_K 125 |
|||
#define GPU_K 126 |
|||
#define USBPHY_K 127 |
|||
#define STGEN_K 128 |
|||
#define SPDIF_K 129 |
|||
#define SPI1_K 130 |
|||
#define SPI2_K 131 |
|||
#define SPI3_K 132 |
|||
#define SPI4_K 133 |
|||
#define SPI5_K 134 |
|||
#define SPI6_K 135 |
|||
#define CEC_K 136 |
|||
#define I2C1_K 137 |
|||
#define I2C2_K 138 |
|||
#define I2C3_K 139 |
|||
#define I2C4_K 140 |
|||
#define I2C5_K 141 |
|||
#define I2C6_K 142 |
|||
#define LPTIM1_K 143 |
|||
#define LPTIM2_K 144 |
|||
#define LPTIM3_K 145 |
|||
#define LPTIM4_K 146 |
|||
#define LPTIM5_K 147 |
|||
#define USART1_K 148 |
|||
#define USART2_K 149 |
|||
#define USART3_K 150 |
|||
#define UART4_K 151 |
|||
#define UART5_K 152 |
|||
#define USART6_K 153 |
|||
#define UART7_K 154 |
|||
#define UART8_K 155 |
|||
#define DFSDM_K 156 |
|||
#define FDCAN_K 157 |
|||
#define SAI1_K 158 |
|||
#define SAI2_K 159 |
|||
#define SAI3_K 160 |
|||
#define SAI4_K 161 |
|||
#define ADC12_K 162 |
|||
#define DSI_K 163 |
|||
#define DSI_PX 164 |
|||
#define ADFSDM_K 165 |
|||
#define USBO_K 166 |
|||
#define LTDC_PX 167 |
|||
#define DAC12_K 168 |
|||
#define ETHPTP_K 169 |
|||
|
|||
/* PLL */ |
|||
#define PLL1 176 |
|||
#define PLL2 177 |
|||
#define PLL3 178 |
|||
#define PLL4 179 |
|||
|
|||
/* ODF */ |
|||
#define PLL1_P 180 |
|||
#define PLL1_Q 181 |
|||
#define PLL1_R 182 |
|||
#define PLL2_P 183 |
|||
#define PLL2_Q 184 |
|||
#define PLL2_R 185 |
|||
#define PLL3_P 186 |
|||
#define PLL3_Q 187 |
|||
#define PLL3_R 188 |
|||
#define PLL4_P 189 |
|||
#define PLL4_Q 190 |
|||
#define PLL4_R 191 |
|||
|
|||
/* AUX */ |
|||
#define RTC 192 |
|||
|
|||
/* MCLK */ |
|||
#define CK_PER 193 |
|||
#define CK_MPU 194 |
|||
#define CK_AXI 195 |
|||
#define CK_MCU 196 |
|||
|
|||
/* Time base */ |
|||
#define TIM2_K 197 |
|||
#define TIM3_K 198 |
|||
#define TIM4_K 199 |
|||
#define TIM5_K 200 |
|||
#define TIM6_K 201 |
|||
#define TIM7_K 202 |
|||
#define TIM12_K 203 |
|||
#define TIM13_K 204 |
|||
#define TIM14_K 205 |
|||
#define TIM1_K 206 |
|||
#define TIM8_K 207 |
|||
#define TIM15_K 208 |
|||
#define TIM16_K 209 |
|||
#define TIM17_K 210 |
|||
|
|||
/* MCO clocks */ |
|||
#define CK_MCO1 211 |
|||
#define CK_MCO2 212 |
|||
|
|||
/* TRACE & DEBUG clocks */ |
|||
#define CK_DBG 214 |
|||
#define CK_TRACE 215 |
|||
|
|||
/* DDR */ |
|||
#define DDRC1 220 |
|||
#define DDRC1LP 221 |
|||
#define DDRC2 222 |
|||
#define DDRC2LP 223 |
|||
#define DDRPHYC 224 |
|||
#define DDRPHYCLP 225 |
|||
#define DDRCAPB 226 |
|||
#define DDRCAPBLP 227 |
|||
#define AXIDCG 228 |
|||
#define DDRPHYCAPB 229 |
|||
#define DDRPHYCAPBLP 230 |
|||
#define DDRPERFM 231 |
|||
|
|||
#define STM32MP1_LAST_CLK 232 |
|||
|
|||
/* SCMI clock identifiers */ |
|||
#define CK_SCMI0_HSE 0 |
|||
#define CK_SCMI0_HSI 1 |
|||
#define CK_SCMI0_CSI 2 |
|||
#define CK_SCMI0_LSE 3 |
|||
#define CK_SCMI0_LSI 4 |
|||
#define CK_SCMI0_PLL2_Q 5 |
|||
#define CK_SCMI0_PLL2_R 6 |
|||
#define CK_SCMI0_MPU 7 |
|||
#define CK_SCMI0_AXI 8 |
|||
#define CK_SCMI0_BSEC 9 |
|||
#define CK_SCMI0_CRYP1 10 |
|||
#define CK_SCMI0_GPIOZ 11 |
|||
#define CK_SCMI0_HASH1 12 |
|||
#define CK_SCMI0_I2C4 13 |
|||
#define CK_SCMI0_I2C6 14 |
|||
#define CK_SCMI0_IWDG1 15 |
|||
#define CK_SCMI0_RNG1 16 |
|||
#define CK_SCMI0_RTC 17 |
|||
#define CK_SCMI0_RTCAPB 18 |
|||
#define CK_SCMI0_SPI6 19 |
|||
#define CK_SCMI0_USART1 20 |
|||
|
|||
#define CK_SCMI1_PLL3_Q 0 |
|||
#define CK_SCMI1_PLL3_R 1 |
|||
#define CK_SCMI1_MCU 2 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ |
|||
@ -0,0 +1,282 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) 2017-2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ |
|||
#define _DT_BINDINGS_CLOCK_STM32MP15_CLKSRC_H_ |
|||
|
|||
/* PLL output is enable when x=1, with x=p,q or r */ |
|||
#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) |
|||
|
|||
/* st,clksrc: mandatory clock source */ |
|||
#define CLK_MPU_HSI 0x00000200 |
|||
#define CLK_MPU_HSE 0x00000201 |
|||
#define CLK_MPU_PLL1P 0x00000202 |
|||
#define CLK_MPU_PLL1P_DIV 0x00000203 |
|||
|
|||
#define CLK_AXI_HSI 0x00000240 |
|||
#define CLK_AXI_HSE 0x00000241 |
|||
#define CLK_AXI_PLL2P 0x00000242 |
|||
|
|||
#define CLK_MCU_HSI 0x00000480 |
|||
#define CLK_MCU_HSE 0x00000481 |
|||
#define CLK_MCU_CSI 0x00000482 |
|||
#define CLK_MCU_PLL3P 0x00000483 |
|||
|
|||
#define CLK_PLL12_HSI 0x00000280 |
|||
#define CLK_PLL12_HSE 0x00000281 |
|||
|
|||
#define CLK_PLL3_HSI 0x00008200 |
|||
#define CLK_PLL3_HSE 0x00008201 |
|||
#define CLK_PLL3_CSI 0x00008202 |
|||
|
|||
#define CLK_PLL4_HSI 0x00008240 |
|||
#define CLK_PLL4_HSE 0x00008241 |
|||
#define CLK_PLL4_CSI 0x00008242 |
|||
#define CLK_PLL4_I2SCKIN 0x00008243 |
|||
|
|||
#define CLK_RTC_DISABLED 0x00001400 |
|||
#define CLK_RTC_LSE 0x00001401 |
|||
#define CLK_RTC_LSI 0x00001402 |
|||
#define CLK_RTC_HSE 0x00001403 |
|||
|
|||
#define CLK_MCO1_HSI 0x00008000 |
|||
#define CLK_MCO1_HSE 0x00008001 |
|||
#define CLK_MCO1_CSI 0x00008002 |
|||
#define CLK_MCO1_LSI 0x00008003 |
|||
#define CLK_MCO1_LSE 0x00008004 |
|||
#define CLK_MCO1_DISABLED 0x0000800F |
|||
|
|||
#define CLK_MCO2_MPU 0x00008040 |
|||
#define CLK_MCO2_AXI 0x00008041 |
|||
#define CLK_MCO2_MCU 0x00008042 |
|||
#define CLK_MCO2_PLL4P 0x00008043 |
|||
#define CLK_MCO2_HSE 0x00008044 |
|||
#define CLK_MCO2_HSI 0x00008045 |
|||
#define CLK_MCO2_DISABLED 0x0000804F |
|||
|
|||
/* st,pkcs: peripheral kernel clock source */ |
|||
|
|||
#define CLK_I2C12_PCLK1 0x00008C00 |
|||
#define CLK_I2C12_PLL4R 0x00008C01 |
|||
#define CLK_I2C12_HSI 0x00008C02 |
|||
#define CLK_I2C12_CSI 0x00008C03 |
|||
#define CLK_I2C12_DISABLED 0x00008C07 |
|||
|
|||
#define CLK_I2C35_PCLK1 0x00008C40 |
|||
#define CLK_I2C35_PLL4R 0x00008C41 |
|||
#define CLK_I2C35_HSI 0x00008C42 |
|||
#define CLK_I2C35_CSI 0x00008C43 |
|||
#define CLK_I2C35_DISABLED 0x00008C47 |
|||
|
|||
#define CLK_I2C46_PCLK5 0x00000C00 |
|||
#define CLK_I2C46_PLL3Q 0x00000C01 |
|||
#define CLK_I2C46_HSI 0x00000C02 |
|||
#define CLK_I2C46_CSI 0x00000C03 |
|||
#define CLK_I2C46_DISABLED 0x00000C07 |
|||
|
|||
#define CLK_SAI1_PLL4Q 0x00008C80 |
|||
#define CLK_SAI1_PLL3Q 0x00008C81 |
|||
#define CLK_SAI1_I2SCKIN 0x00008C82 |
|||
#define CLK_SAI1_CKPER 0x00008C83 |
|||
#define CLK_SAI1_PLL3R 0x00008C84 |
|||
#define CLK_SAI1_DISABLED 0x00008C87 |
|||
|
|||
#define CLK_SAI2_PLL4Q 0x00008CC0 |
|||
#define CLK_SAI2_PLL3Q 0x00008CC1 |
|||
#define CLK_SAI2_I2SCKIN 0x00008CC2 |
|||
#define CLK_SAI2_CKPER 0x00008CC3 |
|||
#define CLK_SAI2_SPDIF 0x00008CC4 |
|||
#define CLK_SAI2_PLL3R 0x00008CC5 |
|||
#define CLK_SAI2_DISABLED 0x00008CC7 |
|||
|
|||
#define CLK_SAI3_PLL4Q 0x00008D00 |
|||
#define CLK_SAI3_PLL3Q 0x00008D01 |
|||
#define CLK_SAI3_I2SCKIN 0x00008D02 |
|||
#define CLK_SAI3_CKPER 0x00008D03 |
|||
#define CLK_SAI3_PLL3R 0x00008D04 |
|||
#define CLK_SAI3_DISABLED 0x00008D07 |
|||
|
|||
#define CLK_SAI4_PLL4Q 0x00008D40 |
|||
#define CLK_SAI4_PLL3Q 0x00008D41 |
|||
#define CLK_SAI4_I2SCKIN 0x00008D42 |
|||
#define CLK_SAI4_CKPER 0x00008D43 |
|||
#define CLK_SAI4_PLL3R 0x00008D44 |
|||
#define CLK_SAI4_DISABLED 0x00008D47 |
|||
|
|||
#define CLK_SPI2S1_PLL4P 0x00008D80 |
|||
#define CLK_SPI2S1_PLL3Q 0x00008D81 |
|||
#define CLK_SPI2S1_I2SCKIN 0x00008D82 |
|||
#define CLK_SPI2S1_CKPER 0x00008D83 |
|||
#define CLK_SPI2S1_PLL3R 0x00008D84 |
|||
#define CLK_SPI2S1_DISABLED 0x00008D87 |
|||
|
|||
#define CLK_SPI2S23_PLL4P 0x00008DC0 |
|||
#define CLK_SPI2S23_PLL3Q 0x00008DC1 |
|||
#define CLK_SPI2S23_I2SCKIN 0x00008DC2 |
|||
#define CLK_SPI2S23_CKPER 0x00008DC3 |
|||
#define CLK_SPI2S23_PLL3R 0x00008DC4 |
|||
#define CLK_SPI2S23_DISABLED 0x00008DC7 |
|||
|
|||
#define CLK_SPI45_PCLK2 0x00008E00 |
|||
#define CLK_SPI45_PLL4Q 0x00008E01 |
|||
#define CLK_SPI45_HSI 0x00008E02 |
|||
#define CLK_SPI45_CSI 0x00008E03 |
|||
#define CLK_SPI45_HSE 0x00008E04 |
|||
#define CLK_SPI45_DISABLED 0x00008E07 |
|||
|
|||
#define CLK_SPI6_PCLK5 0x00000C40 |
|||
#define CLK_SPI6_PLL4Q 0x00000C41 |
|||
#define CLK_SPI6_HSI 0x00000C42 |
|||
#define CLK_SPI6_CSI 0x00000C43 |
|||
#define CLK_SPI6_HSE 0x00000C44 |
|||
#define CLK_SPI6_PLL3Q 0x00000C45 |
|||
#define CLK_SPI6_DISABLED 0x00000C47 |
|||
|
|||
#define CLK_UART6_PCLK2 0x00008E40 |
|||
#define CLK_UART6_PLL4Q 0x00008E41 |
|||
#define CLK_UART6_HSI 0x00008E42 |
|||
#define CLK_UART6_CSI 0x00008E43 |
|||
#define CLK_UART6_HSE 0x00008E44 |
|||
#define CLK_UART6_DISABLED 0x00008E47 |
|||
|
|||
#define CLK_UART24_PCLK1 0x00008E80 |
|||
#define CLK_UART24_PLL4Q 0x00008E81 |
|||
#define CLK_UART24_HSI 0x00008E82 |
|||
#define CLK_UART24_CSI 0x00008E83 |
|||
#define CLK_UART24_HSE 0x00008E84 |
|||
#define CLK_UART24_DISABLED 0x00008E87 |
|||
|
|||
#define CLK_UART35_PCLK1 0x00008EC0 |
|||
#define CLK_UART35_PLL4Q 0x00008EC1 |
|||
#define CLK_UART35_HSI 0x00008EC2 |
|||
#define CLK_UART35_CSI 0x00008EC3 |
|||
#define CLK_UART35_HSE 0x00008EC4 |
|||
#define CLK_UART35_DISABLED 0x00008EC7 |
|||
|
|||
#define CLK_UART78_PCLK1 0x00008F00 |
|||
#define CLK_UART78_PLL4Q 0x00008F01 |
|||
#define CLK_UART78_HSI 0x00008F02 |
|||
#define CLK_UART78_CSI 0x00008F03 |
|||
#define CLK_UART78_HSE 0x00008F04 |
|||
#define CLK_UART78_DISABLED 0x00008F07 |
|||
|
|||
#define CLK_UART1_PCLK5 0x00000C80 |
|||
#define CLK_UART1_PLL3Q 0x00000C81 |
|||
#define CLK_UART1_HSI 0x00000C82 |
|||
#define CLK_UART1_CSI 0x00000C83 |
|||
#define CLK_UART1_PLL4Q 0x00000C84 |
|||
#define CLK_UART1_HSE 0x00000C85 |
|||
#define CLK_UART1_DISABLED 0x00000C87 |
|||
|
|||
#define CLK_SDMMC12_HCLK6 0x00008F40 |
|||
#define CLK_SDMMC12_PLL3R 0x00008F41 |
|||
#define CLK_SDMMC12_PLL4P 0x00008F42 |
|||
#define CLK_SDMMC12_HSI 0x00008F43 |
|||
#define CLK_SDMMC12_DISABLED 0x00008F47 |
|||
|
|||
#define CLK_SDMMC3_HCLK2 0x00008F80 |
|||
#define CLK_SDMMC3_PLL3R 0x00008F81 |
|||
#define CLK_SDMMC3_PLL4P 0x00008F82 |
|||
#define CLK_SDMMC3_HSI 0x00008F83 |
|||
#define CLK_SDMMC3_DISABLED 0x00008F87 |
|||
|
|||
#define CLK_ETH_PLL4P 0x00008FC0 |
|||
#define CLK_ETH_PLL3Q 0x00008FC1 |
|||
#define CLK_ETH_DISABLED 0x00008FC3 |
|||
|
|||
#define CLK_QSPI_ACLK 0x00009000 |
|||
#define CLK_QSPI_PLL3R 0x00009001 |
|||
#define CLK_QSPI_PLL4P 0x00009002 |
|||
#define CLK_QSPI_CKPER 0x00009003 |
|||
|
|||
#define CLK_FMC_ACLK 0x00009040 |
|||
#define CLK_FMC_PLL3R 0x00009041 |
|||
#define CLK_FMC_PLL4P 0x00009042 |
|||
#define CLK_FMC_CKPER 0x00009043 |
|||
|
|||
#define CLK_FDCAN_HSE 0x000090C0 |
|||
#define CLK_FDCAN_PLL3Q 0x000090C1 |
|||
#define CLK_FDCAN_PLL4Q 0x000090C2 |
|||
#define CLK_FDCAN_PLL4R 0x000090C3 |
|||
|
|||
#define CLK_SPDIF_PLL4P 0x00009140 |
|||
#define CLK_SPDIF_PLL3Q 0x00009141 |
|||
#define CLK_SPDIF_HSI 0x00009142 |
|||
#define CLK_SPDIF_DISABLED 0x00009143 |
|||
|
|||
#define CLK_CEC_LSE 0x00009180 |
|||
#define CLK_CEC_LSI 0x00009181 |
|||
#define CLK_CEC_CSI_DIV122 0x00009182 |
|||
#define CLK_CEC_DISABLED 0x00009183 |
|||
|
|||
#define CLK_USBPHY_HSE 0x000091C0 |
|||
#define CLK_USBPHY_PLL4R 0x000091C1 |
|||
#define CLK_USBPHY_HSE_DIV2 0x000091C2 |
|||
#define CLK_USBPHY_DISABLED 0x000091C3 |
|||
|
|||
#define CLK_USBO_PLL4R 0x800091C0 |
|||
#define CLK_USBO_USBPHY 0x800091C1 |
|||
|
|||
#define CLK_RNG1_CSI 0x00000CC0 |
|||
#define CLK_RNG1_PLL4R 0x00000CC1 |
|||
#define CLK_RNG1_LSE 0x00000CC2 |
|||
#define CLK_RNG1_LSI 0x00000CC3 |
|||
|
|||
#define CLK_RNG2_CSI 0x00009200 |
|||
#define CLK_RNG2_PLL4R 0x00009201 |
|||
#define CLK_RNG2_LSE 0x00009202 |
|||
#define CLK_RNG2_LSI 0x00009203 |
|||
|
|||
#define CLK_CKPER_HSI 0x00000D00 |
|||
#define CLK_CKPER_CSI 0x00000D01 |
|||
#define CLK_CKPER_HSE 0x00000D02 |
|||
#define CLK_CKPER_DISABLED 0x00000D03 |
|||
|
|||
#define CLK_STGEN_HSI 0x00000D40 |
|||
#define CLK_STGEN_HSE 0x00000D41 |
|||
#define CLK_STGEN_DISABLED 0x00000D43 |
|||
|
|||
#define CLK_DSI_DSIPLL 0x00009240 |
|||
#define CLK_DSI_PLL4P 0x00009241 |
|||
|
|||
#define CLK_ADC_PLL4R 0x00009280 |
|||
#define CLK_ADC_CKPER 0x00009281 |
|||
#define CLK_ADC_PLL3Q 0x00009282 |
|||
#define CLK_ADC_DISABLED 0x00009283 |
|||
|
|||
#define CLK_LPTIM45_PCLK3 0x000092C0 |
|||
#define CLK_LPTIM45_PLL4P 0x000092C1 |
|||
#define CLK_LPTIM45_PLL3Q 0x000092C2 |
|||
#define CLK_LPTIM45_LSE 0x000092C3 |
|||
#define CLK_LPTIM45_LSI 0x000092C4 |
|||
#define CLK_LPTIM45_CKPER 0x000092C5 |
|||
#define CLK_LPTIM45_DISABLED 0x000092C7 |
|||
|
|||
#define CLK_LPTIM23_PCLK3 0x00009300 |
|||
#define CLK_LPTIM23_PLL4Q 0x00009301 |
|||
#define CLK_LPTIM23_CKPER 0x00009302 |
|||
#define CLK_LPTIM23_LSE 0x00009303 |
|||
#define CLK_LPTIM23_LSI 0x00009304 |
|||
#define CLK_LPTIM23_DISABLED 0x00009307 |
|||
|
|||
#define CLK_LPTIM1_PCLK1 0x00009340 |
|||
#define CLK_LPTIM1_PLL4P 0x00009341 |
|||
#define CLK_LPTIM1_PLL3Q 0x00009342 |
|||
#define CLK_LPTIM1_LSE 0x00009343 |
|||
#define CLK_LPTIM1_LSI 0x00009344 |
|||
#define CLK_LPTIM1_CKPER 0x00009345 |
|||
#define CLK_LPTIM1_DISABLED 0x00009347 |
|||
|
|||
/* define for st,pll /csg */ |
|||
#define SSCG_MODE_CENTER_SPREAD 0 |
|||
#define SSCG_MODE_DOWN_SPREAD 1 |
|||
|
|||
/* define for st,drive */ |
|||
#define LSEDRV_LOWEST 0 |
|||
#define LSEDRV_MEDIUM_LOW 1 |
|||
#define LSEDRV_MEDIUM_HIGH 2 |
|||
#define LSEDRV_HIGHEST 3 |
|||
|
|||
#endif |
|||
@ -1,121 +1,11 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ |
|||
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2018 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
* Copyright (C) 2020-2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP1_RESET_H_ |
|||
#define _DT_BINDINGS_STM32MP1_RESET_H_ |
|||
|
|||
#define LTDC_R 3072 |
|||
#define DSI_R 3076 |
|||
#define DDRPERFM_R 3080 |
|||
#define USBPHY_R 3088 |
|||
#define SPI6_R 3136 |
|||
#define I2C4_R 3138 |
|||
#define I2C6_R 3139 |
|||
#define USART1_R 3140 |
|||
#define STGEN_R 3156 |
|||
#define GPIOZ_R 3200 |
|||
#define CRYP1_R 3204 |
|||
#define HASH1_R 3205 |
|||
#define RNG1_R 3206 |
|||
#define AXIM_R 3216 |
|||
#define GPU_R 3269 |
|||
#define ETHMAC_R 3274 |
|||
#define FMC_R 3276 |
|||
#define QSPI_R 3278 |
|||
#define SDMMC1_R 3280 |
|||
#define SDMMC2_R 3281 |
|||
#define CRC1_R 3284 |
|||
#define USBH_R 3288 |
|||
#define MDMA_R 3328 |
|||
#define MCU_R 8225 |
|||
#define TIM2_R 19456 |
|||
#define TIM3_R 19457 |
|||
#define TIM4_R 19458 |
|||
#define TIM5_R 19459 |
|||
#define TIM6_R 19460 |
|||
#define TIM7_R 19461 |
|||
#define TIM12_R 16462 |
|||
#define TIM13_R 16463 |
|||
#define TIM14_R 16464 |
|||
#define LPTIM1_R 19465 |
|||
#define SPI2_R 19467 |
|||
#define SPI3_R 19468 |
|||
#define USART2_R 19470 |
|||
#define USART3_R 19471 |
|||
#define UART4_R 19472 |
|||
#define UART5_R 19473 |
|||
#define UART7_R 19474 |
|||
#define UART8_R 19475 |
|||
#define I2C1_R 19477 |
|||
#define I2C2_R 19478 |
|||
#define I2C3_R 19479 |
|||
#define I2C5_R 19480 |
|||
#define SPDIF_R 19482 |
|||
#define CEC_R 19483 |
|||
#define DAC12_R 19485 |
|||
#define MDIO_R 19847 |
|||
#define TIM1_R 19520 |
|||
#define TIM8_R 19521 |
|||
#define TIM15_R 19522 |
|||
#define TIM16_R 19523 |
|||
#define TIM17_R 19524 |
|||
#define SPI1_R 19528 |
|||
#define SPI4_R 19529 |
|||
#define SPI5_R 19530 |
|||
#define USART6_R 19533 |
|||
#define SAI1_R 19536 |
|||
#define SAI2_R 19537 |
|||
#define SAI3_R 19538 |
|||
#define DFSDM_R 19540 |
|||
#define FDCAN_R 19544 |
|||
#define LPTIM2_R 19584 |
|||
#define LPTIM3_R 19585 |
|||
#define LPTIM4_R 19586 |
|||
#define LPTIM5_R 19587 |
|||
#define SAI4_R 19592 |
|||
#define SYSCFG_R 19595 |
|||
#define VREF_R 19597 |
|||
#define TMPSENS_R 19600 |
|||
#define PMBCTRL_R 19601 |
|||
#define DMA1_R 19648 |
|||
#define DMA2_R 19649 |
|||
#define DMAMUX_R 19650 |
|||
#define ADC12_R 19653 |
|||
#define USBO_R 19656 |
|||
#define SDMMC3_R 19664 |
|||
#define CAMITF_R 19712 |
|||
#define CRYP2_R 19716 |
|||
#define HASH2_R 19717 |
|||
#define RNG2_R 19718 |
|||
#define CRC2_R 19719 |
|||
#define HSEM_R 19723 |
|||
#define MBOX_R 19724 |
|||
#define GPIOA_R 19776 |
|||
#define GPIOB_R 19777 |
|||
#define GPIOC_R 19778 |
|||
#define GPIOD_R 19779 |
|||
#define GPIOE_R 19780 |
|||
#define GPIOF_R 19781 |
|||
#define GPIOG_R 19782 |
|||
#define GPIOH_R 19783 |
|||
#define GPIOI_R 19784 |
|||
#define GPIOJ_R 19785 |
|||
#define GPIOK_R 19786 |
|||
|
|||
/* SCMI reset domain identifiers */ |
|||
#define RST_SCMI0_SPI6 0 |
|||
#define RST_SCMI0_I2C4 1 |
|||
#define RST_SCMI0_I2C6 2 |
|||
#define RST_SCMI0_USART1 3 |
|||
#define RST_SCMI0_STGEN 4 |
|||
#define RST_SCMI0_GPIOZ 5 |
|||
#define RST_SCMI0_CRYP1 6 |
|||
#define RST_SCMI0_HASH1 7 |
|||
#define RST_SCMI0_RNG1 8 |
|||
#define RST_SCMI0_MDMA 9 |
|||
#define RST_SCMI0_MCU 10 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */ |
|||
#if STM32MP13 |
|||
#include "stm32mp13-resets.h" |
|||
#endif |
|||
#if STM32MP15 |
|||
#include "stm32mp15-resets.h" |
|||
#endif |
|||
|
|||
@ -0,0 +1,96 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP13_RESET_H_ |
|||
#define _DT_BINDINGS_STM32MP13_RESET_H_ |
|||
|
|||
#define TIM2_R 13568 |
|||
#define TIM3_R 13569 |
|||
#define TIM4_R 13570 |
|||
#define TIM5_R 13571 |
|||
#define TIM6_R 13572 |
|||
#define TIM7_R 13573 |
|||
#define LPTIM1_R 13577 |
|||
#define SPI2_R 13579 |
|||
#define SPI3_R 13580 |
|||
#define USART3_R 13583 |
|||
#define UART4_R 13584 |
|||
#define UART5_R 13585 |
|||
#define UART7_R 13586 |
|||
#define UART8_R 13587 |
|||
#define I2C1_R 13589 |
|||
#define I2C2_R 13590 |
|||
#define SPDIF_R 13594 |
|||
#define TIM1_R 13632 |
|||
#define TIM8_R 13633 |
|||
#define SPI1_R 13640 |
|||
#define USART6_R 13645 |
|||
#define SAI1_R 13648 |
|||
#define SAI2_R 13649 |
|||
#define DFSDM_R 13652 |
|||
#define FDCAN_R 13656 |
|||
#define LPTIM2_R 13696 |
|||
#define LPTIM3_R 13697 |
|||
#define LPTIM4_R 13698 |
|||
#define LPTIM5_R 13699 |
|||
#define SYSCFG_R 13707 |
|||
#define VREF_R 13709 |
|||
#define DTS_R 13712 |
|||
#define PMBCTRL_R 13713 |
|||
#define LTDC_R 13760 |
|||
#define DCMIPP_R 13761 |
|||
#define DDRPERFM_R 13768 |
|||
#define USBPHY_R 13776 |
|||
#define STGEN_R 13844 |
|||
#define USART1_R 13888 |
|||
#define USART2_R 13889 |
|||
#define SPI4_R 13890 |
|||
#define SPI5_R 13891 |
|||
#define I2C3_R 13892 |
|||
#define I2C4_R 13893 |
|||
#define I2C5_R 13894 |
|||
#define TIM12_R 13895 |
|||
#define TIM13_R 13896 |
|||
#define TIM14_R 13897 |
|||
#define TIM15_R 13898 |
|||
#define TIM16_R 13899 |
|||
#define TIM17_R 13900 |
|||
#define DMA1_R 13952 |
|||
#define DMA2_R 13953 |
|||
#define DMAMUX1_R 13954 |
|||
#define DMA3_R 13955 |
|||
#define DMAMUX2_R 13956 |
|||
#define ADC1_R 13957 |
|||
#define ADC2_R 13958 |
|||
#define USBO_R 13960 |
|||
#define GPIOA_R 14080 |
|||
#define GPIOB_R 14081 |
|||
#define GPIOC_R 14082 |
|||
#define GPIOD_R 14083 |
|||
#define GPIOE_R 14084 |
|||
#define GPIOF_R 14085 |
|||
#define GPIOG_R 14086 |
|||
#define GPIOH_R 14087 |
|||
#define GPIOI_R 14088 |
|||
#define TSC_R 14095 |
|||
#define PKA_R 14146 |
|||
#define SAES_R 14147 |
|||
#define CRYP1_R 14148 |
|||
#define HASH1_R 14149 |
|||
#define RNG1_R 14150 |
|||
#define AXIMC_R 14160 |
|||
#define MDMA_R 14208 |
|||
#define MCE_R 14209 |
|||
#define ETH1MAC_R 14218 |
|||
#define FMC_R 14220 |
|||
#define QSPI_R 14222 |
|||
#define SDMMC1_R 14224 |
|||
#define SDMMC2_R 14225 |
|||
#define CRC1_R 14228 |
|||
#define USBH_R 14232 |
|||
#define ETH2MAC_R 14238 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP13_RESET_H_ */ |
|||
@ -0,0 +1,123 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ |
|||
/*
|
|||
* Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved |
|||
* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP15_RESET_H_ |
|||
#define _DT_BINDINGS_STM32MP15_RESET_H_ |
|||
|
|||
#define MCU_HOLD_BOOT_R 2144 |
|||
#define LTDC_R 3072 |
|||
#define DSI_R 3076 |
|||
#define DDRPERFM_R 3080 |
|||
#define USBPHY_R 3088 |
|||
#define SPI6_R 3136 |
|||
#define I2C4_R 3138 |
|||
#define I2C6_R 3139 |
|||
#define USART1_R 3140 |
|||
#define STGEN_R 3156 |
|||
#define GPIOZ_R 3200 |
|||
#define CRYP1_R 3204 |
|||
#define HASH1_R 3205 |
|||
#define RNG1_R 3206 |
|||
#define AXIM_R 3216 |
|||
#define GPU_R 3269 |
|||
#define ETHMAC_R 3274 |
|||
#define FMC_R 3276 |
|||
#define QSPI_R 3278 |
|||
#define SDMMC1_R 3280 |
|||
#define SDMMC2_R 3281 |
|||
#define CRC1_R 3284 |
|||
#define USBH_R 3288 |
|||
#define MDMA_R 3328 |
|||
#define MCU_R 8225 |
|||
#define TIM2_R 19456 |
|||
#define TIM3_R 19457 |
|||
#define TIM4_R 19458 |
|||
#define TIM5_R 19459 |
|||
#define TIM6_R 19460 |
|||
#define TIM7_R 19461 |
|||
#define TIM12_R 16462 |
|||
#define TIM13_R 16463 |
|||
#define TIM14_R 16464 |
|||
#define LPTIM1_R 19465 |
|||
#define SPI2_R 19467 |
|||
#define SPI3_R 19468 |
|||
#define USART2_R 19470 |
|||
#define USART3_R 19471 |
|||
#define UART4_R 19472 |
|||
#define UART5_R 19473 |
|||
#define UART7_R 19474 |
|||
#define UART8_R 19475 |
|||
#define I2C1_R 19477 |
|||
#define I2C2_R 19478 |
|||
#define I2C3_R 19479 |
|||
#define I2C5_R 19480 |
|||
#define SPDIF_R 19482 |
|||
#define CEC_R 19483 |
|||
#define DAC12_R 19485 |
|||
#define MDIO_R 19847 |
|||
#define TIM1_R 19520 |
|||
#define TIM8_R 19521 |
|||
#define TIM15_R 19522 |
|||
#define TIM16_R 19523 |
|||
#define TIM17_R 19524 |
|||
#define SPI1_R 19528 |
|||
#define SPI4_R 19529 |
|||
#define SPI5_R 19530 |
|||
#define USART6_R 19533 |
|||
#define SAI1_R 19536 |
|||
#define SAI2_R 19537 |
|||
#define SAI3_R 19538 |
|||
#define DFSDM_R 19540 |
|||
#define FDCAN_R 19544 |
|||
#define LPTIM2_R 19584 |
|||
#define LPTIM3_R 19585 |
|||
#define LPTIM4_R 19586 |
|||
#define LPTIM5_R 19587 |
|||
#define SAI4_R 19592 |
|||
#define SYSCFG_R 19595 |
|||
#define VREF_R 19597 |
|||
#define TMPSENS_R 19600 |
|||
#define PMBCTRL_R 19601 |
|||
#define DMA1_R 19648 |
|||
#define DMA2_R 19649 |
|||
#define DMAMUX_R 19650 |
|||
#define ADC12_R 19653 |
|||
#define USBO_R 19656 |
|||
#define SDMMC3_R 19664 |
|||
#define CAMITF_R 19712 |
|||
#define CRYP2_R 19716 |
|||
#define HASH2_R 19717 |
|||
#define RNG2_R 19718 |
|||
#define CRC2_R 19719 |
|||
#define HSEM_R 19723 |
|||
#define MBOX_R 19724 |
|||
#define GPIOA_R 19776 |
|||
#define GPIOB_R 19777 |
|||
#define GPIOC_R 19778 |
|||
#define GPIOD_R 19779 |
|||
#define GPIOE_R 19780 |
|||
#define GPIOF_R 19781 |
|||
#define GPIOG_R 19782 |
|||
#define GPIOH_R 19783 |
|||
#define GPIOI_R 19784 |
|||
#define GPIOJ_R 19785 |
|||
#define GPIOK_R 19786 |
|||
|
|||
/* SCMI reset domain identifiers */ |
|||
#define RST_SCMI0_SPI6 0 |
|||
#define RST_SCMI0_I2C4 1 |
|||
#define RST_SCMI0_I2C6 2 |
|||
#define RST_SCMI0_USART1 3 |
|||
#define RST_SCMI0_STGEN 4 |
|||
#define RST_SCMI0_GPIOZ 5 |
|||
#define RST_SCMI0_CRYP1 6 |
|||
#define RST_SCMI0_HASH1 7 |
|||
#define RST_SCMI0_RNG1 8 |
|||
#define RST_SCMI0_MDMA 9 |
|||
#define RST_SCMI0_MCU 10 |
|||
#define RST_SCMI0_MCU_HOLD_BOOT 11 |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */ |
|||
@ -0,0 +1,35 @@ |
|||
/*
|
|||
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause |
|||
* |
|||
* Copyright (C) 2022, STMicroelectronics - All Rights Reserved |
|||
*/ |
|||
|
|||
#ifndef _DT_BINDINGS_STM32MP13_TZC400_H |
|||
#define _DT_BINDINGS_STM32MP13_TZC400_H |
|||
|
|||
#include <drivers/arm/tzc_common.h> |
|||
|
|||
#define STM32MP1_TZC_A7_ID U(0) |
|||
#define STM32MP1_TZC_LCD_ID U(3) |
|||
#define STM32MP1_TZC_MDMA_ID U(5) |
|||
#define STM32MP1_TZC_DMA_ID U(6) |
|||
#define STM32MP1_TZC_USB_HOST_ID U(7) |
|||
#define STM32MP1_TZC_USB_OTG_ID U(8) |
|||
#define STM32MP1_TZC_SDMMC_ID U(9) |
|||
#define STM32MP1_TZC_ETH_ID U(10) |
|||
#define STM32MP1_TZC_DCMIPP_ID U(11) |
|||
#define STM32MP1_TZC_DAP_ID U(15) |
|||
|
|||
#define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ |
|||
(TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DCMIPP_ID) | \ |
|||
TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)) |
|||
|
|||
#endif /* _DT_BINDINGS_STM32MP13_TZC400_H */ |
|||
Loading…
Reference in new issue