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chore: rename hunter to a720 

Rename cortex_hunter to cortex_a720

Change-Id: Id4e0e2cd47051c2e92b3f16373ea06ef4df1d75f
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
pull/1999/head
Govindraj Raja 1 year ago
parent
870fcb9495
commit
31b3945527
6 changed files with 43 additions and 43 deletions
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  1. 4
      docs/plat/arm/tc/index.rst
  2. 2
      docs/security_advisories/security-advisory-tfv-9.rst
  3. 20
      include/lib/cpus/aarch64/cortex_a720.h
  4. 56
      lib/cpus/aarch64/cortex_a720.S
  5. 2
      plat/arm/board/arm_fpga/platform.mk
  6. 2
      plat/arm/board/tc/platform.mk

4
docs/plat/arm/tc/index.rst
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@ -19,7 +19,7 @@ is the CPUs supported as below:
- TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated) - TC0 has support for Cortex A510, Cortex A710 and Cortex X2. (Note TC0 is now deprecated)
- TC1 has support for Cortex A510, Cortex Makalu and Cortex X3. - TC1 has support for Cortex A510, Cortex Makalu and Cortex X3.
- TC2 has support for Hayes and Hunter Arm CPUs. - TC2 has support for Hayes and Cortex A720 Arm CPUs.
Boot Sequence Boot Sequence
@ -58,6 +58,6 @@ Build Procedure (TF-A only)
-------------- --------------
*Copyright (c) 2020-2022, Arm Limited. All rights reserved.* *Copyright (c) 2020-2023, Arm Limited. All rights reserved.*
.. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads .. _Arm Toolchain: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads

2
docs/security_advisories/security-advisory-tfv-9.rst
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@ -77,7 +77,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+ +----------------------+
| Cortex-A715 | | Cortex-A715 |
+----------------------+ +----------------------+
| Cortex-Hunter | | Cortex-A720 |
+----------------------+ +----------------------+
| Neoverse-N1 | | Neoverse-N1 |
+----------------------+ +----------------------+

20
include/lib/cpus/aarch64/cortex_hunter.h → include/lib/cpus/aarch64/cortex_a720.h
View File

@ -1,26 +1,26 @@
/* /*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#ifndef CORTEX_HUNTER_H #ifndef CORTEX_A720_H
#define CORTEX_HUNTER_H #define CORTEX_A720_H
#define CORTEX_HUNTER_MIDR U(0x410FD810) #define CORTEX_A720_MIDR U(0x410FD810)
/* Cortex Hunter loop count for CVE-2022-23960 mitigation */ /* Cortex A720 loop count for CVE-2022-23960 mitigation */
#define CORTEX_HUNTER_BHB_LOOP_COUNT U(132) #define CORTEX_A720_BHB_LOOP_COUNT U(132)
/******************************************************************************* /*******************************************************************************
* CPU Extended Control register specific definitions * CPU Extended Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_HUNTER_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4
/******************************************************************************* /*******************************************************************************
* CPU Power Control register specific definitions * CPU Power Control register specific definitions
******************************************************************************/ ******************************************************************************/
#define CORTEX_HUNTER_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* CORTEX_HUNTER_H */ #endif /* CORTEX_A720_H */

56
lib/cpus/aarch64/cortex_hunter.S → lib/cpus/aarch64/cortex_a720.S
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021-2022, Arm Limited. All rights reserved. * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,23 +7,23 @@
#include <arch.h> #include <arch.h>
#include <asm_macros.S> #include <asm_macros.S>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <cortex_hunter.h> #include <cortex_a720.h>
#include <cpu_macros.S> #include <cpu_macros.S>
#include <plat_macros.S> #include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S" #include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */ /* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0 #if HW_ASSISTED_COHERENCY == 0
#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled" #error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif #endif
/* 64-bit only core */ /* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1 #if CTX_INCLUDE_AARCH32_REGS == 1
#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
#if WORKAROUND_CVE_2022_23960 #if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table CORTEX_HUNTER_BHB_LOOP_COUNT, cortex_hunter wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */ #endif /* WORKAROUND_CVE_2022_23960 */
func check_errata_cve_2022_23960 func check_errata_cve_2022_23960
@ -35,44 +35,44 @@ func check_errata_cve_2022_23960
ret ret
endfunc check_errata_cve_2022_23960 endfunc check_errata_cve_2022_23960
func cortex_hunter_reset_func func cortex_a720_reset_func
/* Disable speculative loads */ /* Disable speculative loads */
msr SSBS, xzr msr SSBS, xzr
#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
/* /*
* The Cortex Hunter generic vectors are overridden to apply errata * The Cortex A720 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs. * mitigation on exception entry from lower ELs.
*/ */
adr x0, wa_cve_vbar_cortex_hunter adr x0, wa_cve_vbar_cortex_a720
msr vbar_el3, x0 msr vbar_el3, x0
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
isb isb
ret ret
endfunc cortex_hunter_reset_func endfunc cortex_a720_reset_func
/* ---------------------------------------------------- /* ----------------------------------------------------
* HW will do the cache maintenance while powering down * HW will do the cache maintenance while powering down
* ---------------------------------------------------- * ----------------------------------------------------
*/ */
func cortex_hunter_core_pwr_dwn func cortex_a720_core_pwr_dwn
/* --------------------------------------------------- /* ---------------------------------------------------
* Enable CPU power down bit in power control register * Enable CPU power down bit in power control register
* --------------------------------------------------- * ---------------------------------------------------
*/ */
mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1 mrs x0, CORTEX_A720_CPUPWRCTLR_EL1
orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0 msr CORTEX_A720_CPUPWRCTLR_EL1, x0
isb isb
ret ret
endfunc cortex_hunter_core_pwr_dwn endfunc cortex_a720_core_pwr_dwn
#if REPORT_ERRATA #if REPORT_ERRATA
/* /*
* Errata printing function for Cortex Hunter. Must follow AAPCS. * Errata printing function for Cortex A720. Must follow AAPCS.
*/ */
func cortex_hunter_errata_report func cortex_a720_errata_report
stp x8, x30, [sp, #-16]! stp x8, x30, [sp, #-16]!
bl cpu_get_rev_var bl cpu_get_rev_var
@ -82,15 +82,15 @@ func cortex_hunter_errata_report
* Report all errata. The revision-variant information is passed to * Report all errata. The revision-variant information is passed to
* checking functions of each errata. * checking functions of each errata.
*/ */
report_errata WORKAROUND_CVE_2022_23960, cortex_hunter, cve_2022_23960 report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960
ldp x8, x30, [sp], #16 ldp x8, x30, [sp], #16
ret ret
endfunc cortex_hunter_errata_report endfunc cortex_a720_errata_report
#endif #endif
/* --------------------------------------------- /* ---------------------------------------------
* This function provides Cortex Hunter-specific * This function provides Cortex A720-specific
* register information for crash reporting. * register information for crash reporting.
* It needs to return with x6 pointing to * It needs to return with x6 pointing to
* a list of register names in ascii and * a list of register names in ascii and
@ -98,16 +98,16 @@ endfunc cortex_hunter_errata_report
* reported. * reported.
* --------------------------------------------- * ---------------------------------------------
*/ */
.section .rodata.cortex_hunter_regs, "aS" .section .rodata.cortex_a720_regs, "aS"
cortex_hunter_regs: /* The ascii list of register names to be reported */ cortex_a720_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", "" .asciz "cpuectlr_el1", ""
func cortex_hunter_cpu_reg_dump func cortex_a720_cpu_reg_dump
adr x6, cortex_hunter_regs adr x6, cortex_a720_regs
mrs x8, CORTEX_HUNTER_CPUECTLR_EL1 mrs x8, CORTEX_A720_CPUECTLR_EL1
ret ret
endfunc cortex_hunter_cpu_reg_dump endfunc cortex_a720_cpu_reg_dump
declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \ declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \
cortex_hunter_reset_func, \ cortex_a720_reset_func, \
cortex_hunter_core_pwr_dwn cortex_a720_core_pwr_dwn

2
plat/arm/board/arm_fpga/platform.mk
View File

@ -61,6 +61,7 @@ else
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \ FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a510.S \
lib/cpus/aarch64/cortex_a710.S \ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_a715.S \ lib/cpus/aarch64/cortex_a715.S \
lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/cortex_x3.S \ lib/cpus/aarch64/cortex_x3.S \
lib/cpus/aarch64/cortex_x4.S \ lib/cpus/aarch64/cortex_x4.S \
lib/cpus/aarch64/neoverse_n_common.S \ lib/cpus/aarch64/neoverse_n_common.S \
@ -68,7 +69,6 @@ else
lib/cpus/aarch64/neoverse_n2.S \ lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \ lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_hayes.S \ lib/cpus/aarch64/cortex_hayes.S \
lib/cpus/aarch64/cortex_hunter.S \
lib/cpus/aarch64/cortex_chaberton.S \ lib/cpus/aarch64/cortex_chaberton.S \
lib/cpus/aarch64/cortex_blackhawk.S lib/cpus/aarch64/cortex_blackhawk.S

2
plat/arm/board/tc/platform.mk
View File

@ -79,7 +79,7 @@ endif
# CPU libraries for TARGET_PLATFORM=2 # CPU libraries for TARGET_PLATFORM=2
ifeq (${TARGET_PLATFORM}, 2) ifeq (${TARGET_PLATFORM}, 2)
TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \ TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \
lib/cpus/aarch64/cortex_hunter.S \ lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/cortex_x4.S lib/cpus/aarch64/cortex_x4.S
endif endif

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