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chore: rename Poseidon to Neoverse V3 

Rename Neoverse Poseidon to Neoverse V3, make changes
to related build flags, macros, file names etc.

Change-Id: I9e40ba8f80b7390703d543787e6cd2ab6301e891
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
pull/2000/merge
Sona Mathew 8 months ago
parent
5f4acf98dd
commit
328d304d27
4 changed files with 101 additions and 101 deletions
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  1. 2
      docs/security_advisories/security-advisory-tfv-9.rst
  2. 20
      include/lib/cpus/aarch64/neoverse_v3.h
  3. 90
      lib/cpus/aarch64/neoverse_poseidon.S
  4. 90
      lib/cpus/aarch64/neoverse_v3.S

2
docs/security_advisories/security-advisory-tfv-9.rst
View File

@ -87,7 +87,7 @@ revisions of Cortex-A73 and Cortex-A75 that implements FEAT_CSV2).
+----------------------+
| Neoverse-V2 |
+----------------------+
| Neoverse-Poseidon |
| Neoverse-V3 |
+----------------------+
For all other cores impacted by Spectre-BHB, some of which that do not implement

20
include/lib/cpus/aarch64/neoverse_poseidon.h → include/lib/cpus/aarch64/neoverse_v3.h
View File

@ -4,25 +4,25 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef NEOVERSE_POSEIDON_H
#define NEOVERSE_POSEIDON_H
#ifndef NEOVERSE_V3_H
#define NEOVERSE_V3_H
#define NEOVERSE_POSEIDON_VNAE_MIDR U(0x410FD830)
#define NEOVERSE_POSEIDON_V_MIDR U(0x410FD840)
#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
#define NEOVERSE_V3_MIDR U(0x410FD840)
/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
/*******************************************************************************
* CPU Extended Control register specific definitions.
******************************************************************************/
#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
#endif /* NEOVERSE_POSEIDON_H */
#endif /* NEOVERSE_V3_H */

90
lib/cpus/aarch64/neoverse_poseidon.S
View File

@ -1,90 +0,0 @@
/*
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_poseidon.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Neoverse-poseidon generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
override_vector_table wa_cve_vbar_neoverse_poseidon
#endif /* IMAGE_BL31 */
workaround_reset_end neoverse_poseidon, CVE(2022,23960)
check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func neoverse_poseidon_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc neoverse_poseidon_core_pwr_dwn
cpu_reset_func_start neoverse_poseidon
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end neoverse_poseidon
errata_report_shim neoverse_poseidon
/* ---------------------------------------------
* This function provides Neoverse-Poseidon specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_poseidon_regs, "aS"
neoverse_poseidon_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_poseidon_cpu_reg_dump
adr x6, neoverse_poseidon_regs
mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
ret
endfunc neoverse_poseidon_cpu_reg_dump
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_VNAE_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn
declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_V_MIDR, \
neoverse_poseidon_reset_func, \
neoverse_poseidon_core_pwr_dwn

90
lib/cpus/aarch64/neoverse_v3.S
View File

@ -0,0 +1,90 @@
/*
* Copyright (c) 2022-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <common/bl_common.h>
#include <neoverse_v3.h>
#include <cpu_macros.S>
#include <plat_macros.S>
#include "wa_cve_2022_23960_bhb_vector.S"
/* Hardware handled coherency */
#if HW_ASSISTED_COHERENCY == 0
#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/* 64-bit only core */
#if CTX_INCLUDE_AARCH32_REGS == 1
#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
#if WORKAROUND_CVE_2022_23960
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
#endif /* WORKAROUND_CVE_2022_23960 */
workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
* The Neoverse V3 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
override_vector_table wa_cve_vbar_neoverse_v3
#endif /* IMAGE_BL31 */
workaround_reset_end neoverse_v3, CVE(2022,23960)
check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func neoverse_v3_core_pwr_dwn
/* ---------------------------------------------
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc neoverse_v3_core_pwr_dwn
cpu_reset_func_start neoverse_v3
/* Disable speculative loads */
msr SSBS, xzr
cpu_reset_func_end neoverse_v3
errata_report_shim neoverse_v3
/* ---------------------------------------------
* This function provides Neoverse V3 specific
* register information for crash reporting.
* It needs to return with x6 pointing to
* a list of register names in ascii and
* x8 - x15 having values of registers to be
* reported.
* ---------------------------------------------
*/
.section .rodata.neoverse_v3_regs, "aS"
neoverse_v3_regs: /* The ascii list of register names to be reported */
.asciz "cpuectlr_el1", ""
func neoverse_v3_cpu_reg_dump
adr x6, neoverse_v3_regs
mrs x8, NEOVERSE_V3_CPUECTLR_EL1
ret
endfunc neoverse_v3_cpu_reg_dump
declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
neoverse_v3_reset_func, \
neoverse_v3_core_pwr_dwn
declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
neoverse_v3_reset_func, \
neoverse_v3_core_pwr_dwn
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