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@ -111,16 +111,21 @@ void bl31_platform_setup(void) |
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} |
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} |
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const mmap_region_t plat_stratix10_mmap[] = { |
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const mmap_region_t plat_stratix10_mmap[] = { |
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), |
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, |
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), |
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MT_MEMORY | MT_RW | MT_NS), |
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_NS), |
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MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, |
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MT_DEVICE | MT_RW | MT_NS), |
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MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, |
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MT_DEVICE | MT_RW | MT_SECURE), |
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, |
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, |
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MT_NON_CACHEABLE | MT_RW | MT_SECURE), |
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MT_NON_CACHEABLE | MT_RW | MT_SECURE), |
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MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, |
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MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, |
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MT_DEVICE | MT_RW | MT_SECURE), |
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MT_DEVICE | MT_RW | MT_SECURE), |
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), |
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, |
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MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), |
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MT_DEVICE | MT_RW | MT_NS), |
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{0}, |
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MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, |
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MT_DEVICE | MT_RW | MT_NS), |
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{0} |
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}; |
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}; |
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/*******************************************************************************
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/*******************************************************************************
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@ -142,7 +147,7 @@ void bl31_plat_arch_setup(void) |
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
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MT_DEVICE | MT_RW | MT_SECURE), |
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MT_DEVICE | MT_RW | MT_SECURE), |
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#endif |
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#endif |
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{0}, |
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{0} |
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}; |
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}; |
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setup_page_tables(bl_regions, plat_stratix10_mmap); |
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setup_page_tables(bl_regions, plat_stratix10_mmap); |
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