Merge changes Id7d4f5df,If82542cc,I0ba80057,I75a443db,Ifa18b4fc, ... into integration

* changes:
  feat(nxp/common/ocram): add driver for OCRAM initialization
  feat(plat/nxp/common): add EESR register definition
  fix(plat/nxp/ls1028a): fix compile error when enable fuse provision
  fix(drivers/nxp/sfp): fix compile warning
  fix(plat/nxp/ls1028a): define endianness of scfg and gpio
  fix(nxp/scfg): fix endianness checking

drivers/nxp/sfp/fuse_prov.c

@@ -326,7 +326,7 @@ static int prog_ospr1(struct fuse_hdr_t *fuse_hdr,
 		      struct sfp_ccsr_regs_t *sfp_ccsr_regs)
 {
 	int ret;
-	uint32_t mask;
+	uint32_t mask = 0;
 
 #ifdef NXP_SFP_VER_3_4
 	if (((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) {

include/drivers/nxp/dcfg/scfg.h

@@ -44,7 +44,7 @@
 #define scfg_clrbits32(a, v)	mmio_clrbits_32((uintptr_t)(a), v)
 #define scfg_clrsetbits32(a, clear, set)	\
 				mmio_clrsetbits_32((uintptr_t)(a), clear, set)
-#elif defined(NXP_GUR_LE)
+#elif defined(NXP_SCFG_LE)
 #define scfg_in32(a)		mmio_read_32((uintptr_t)(a))
 #define scfg_out32(a, v)	mmio_write_32((uintptr_t)(a), v)
 #define scfg_setbits32(a, v)	mmio_setbits_32((uintptr_t)(a), v)

plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h

@@ -56,6 +56,11 @@
 #define RCPM_POWMGTCSR_OFFSET		0x130
 #define RCPM_IPPDEXPCR0_OFFSET		0x140
 #define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
-#endif
+#endif /* NXP_RCPM_ADDR */
+
+#define DCFG_SBEESR2_ADDR		0x20140534
+#define DCFG_MBEESR2_ADDR		0x20140544
+/* SBEESR and MBEESR bit mask */
+#define OCRAM_EESR_MASK			0x00000060
 
 #endif	/*	SOC_DEFAULT_HELPER_MACROS_H	*/

plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h

@@ -79,4 +79,9 @@
 #define ENABLE_WUO			0x10
 #endif /* NXP_CCN_ADDR */
 
+#define DCFG_SBEESR2_ADDR		0x00100534
+#define DCFG_MBEESR2_ADDR		0x00100544
+/* SBEESR and MBEESR bit mask */
+#define OCRAM_EESR_MASK			0x00000008
+
 #endif	/*	SOC_DEFAULT_HELPER_MACROS_H	*/

plat/nxp/common/ocram/aarch64/ocram.S

@@ -0,0 +1,71 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <asm_macros.S>
+
+#include <soc_default_base_addr.h>
+#include <soc_default_helper_macros.h>
+
+.global ocram_init
+
+/*
+ * void ocram_init(uintptr_t start_addr, size_t size)
+ *
+ * This function will do OCRAM ECC.
+ * OCRAM is initialized with 64-bit writes and then a write
+ * performed to address 0x0010_0534 with the value 0x0000_0008.
+ *
+ * x0: start_addr
+ * x1: size in bytes
+ * Called from C
+ */
+
+func ocram_init
+	/* save the aarch32/64 non-volatile registers */
+	stp	x4,  x5,  [sp, #-16]!
+	stp	x6,  x7,  [sp, #-16]!
+	stp	x8,  x9,  [sp, #-16]!
+	stp	x10, x11, [sp, #-16]!
+	stp	x12, x13, [sp, #-16]!
+	stp	x18, x30, [sp, #-16]!
+
+	/* convert bytes to 64-byte chunks */
+	lsr	x1, x1, #6
+1:
+	/* for each location, read and write-back */
+	dc	ivac, x0
+	dsb	sy
+	ldp	x4, x5, [x0]
+	ldp	x6, x7, [x0, #16]
+	ldp	x8, x9, [x0, #32]
+	ldp	x10, x11, [x0, #48]
+	stp	x4, x5, [x0]
+	stp	x6, x7, [x0, #16]
+	stp	x8, x9, [x0, #32]
+	stp	x10, x11, [x0, #48]
+	dc	cvac, x0
+
+	sub	x1, x1, #1
+	cbz	x1, 2f
+	add	x0, x0, #64
+	b	1b
+2:
+	/* Clear OCRAM ECC status bit in SBEESR2 and MBEESR2 */
+	ldr	w1, =OCRAM_EESR_MASK
+	ldr	x0, =DCFG_SBEESR2_ADDR
+	str	w1, [x0]
+	ldr	x0, =DCFG_MBEESR2_ADDR
+	str	w1, [x0]
+
+	/* restore the aarch32/64 non-volatile registers */
+	ldp	x18, x30, [sp], #16
+	ldp	x12, x13, [sp], #16
+	ldp	x10, x11, [sp], #16
+	ldp	x8,  x9,  [sp], #16
+	ldp	x6,  x7,  [sp], #16
+	ldp	x4,  x5,  [sp], #16
+	ret
+endfunc ocram_init

plat/nxp/common/ocram/ocram.h

@@ -0,0 +1,13 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef OCRAM_H
+#define OCRAM_H
+
+void ocram_init(uintptr_t start_addr, size_t size);
+
+#endif /* OCRAM_H */

plat/nxp/common/ocram/ocram.mk

@@ -0,0 +1,14 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+PLAT_OCRAM_PATH		:= $(PLAT_COMMON_PATH)/ocram
+
+OCRAM_SOURCES		:= ${PLAT_OCRAM_PATH}/$(ARCH)/ocram.S
+
+BL2_SOURCES		+= ${OCRAM_SOURCES}
+
+PLAT_INCLUDES           += -I${PLAT_COMMON_PATH}/ocram

plat/nxp/common/plat_make_helper/soc_common_def.mk

@@ -112,3 +112,8 @@ endif
 ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
 $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
 endif
+
+ifeq (${OCRAM_ECC_EN},yes)
+$(eval $(call add_define,CONFIG_OCRAM_ECC_EN))
+include ${PLAT_COMMON_PATH}/ocram/ocram.mk
+endif

plat/nxp/soc-ls1028a/soc.c

@@ -16,6 +16,9 @@
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <ls_interconnect.h>
 #include <mmio.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <nxp_gpio.h>
+#endif
 #if TRUSTED_BOARD_BOOT
 #include <nxp_smmu.h>
 #endif
@@ -81,6 +84,15 @@ unsigned int plat_get_syscnt_freq2(void)
 }
 
 #ifdef IMAGE_BL2
+
+#ifdef POLICY_FUSE_PROVISION
+static gpio_init_info_t gpio_init_data = {
+	.gpio1_base_addr = NXP_GPIO1_ADDR,
+	.gpio2_base_addr = NXP_GPIO2_ADDR,
+	.gpio3_base_addr = NXP_GPIO3_ADDR,
+};
+#endif
+
 void soc_preload_setup(void)
 {
 }

plat/nxp/soc-ls1028a/soc.def

@@ -88,6 +88,8 @@ NXP_SNVS_ENDIANNESS	:=	LE
 NXP_ESDHC_ENDIANNESS	:=	LE
 NXP_QSPI_ENDIANNESS	:=	LE
 NXP_FSPI_ENDIANNESS	:=	LE
+NXP_SCFG_ENDIANNESS	:=	LE
+NXP_GPIO_ENDIANNESS	:=	LE
 
 NXP_SFP_VER		:=	3_4