fix(fdts stm32mp1): set ETH clock on PLL4P on ST boards

Set Ethernet source clock on PLL4P. This is required to enable PTP. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Ia64fbb681d3f04f2b90f373c5eb044f5daa2836c
4 years ago · 3e881a8834
2 changed files with 2 additions and 2 deletions
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@ -232,7 +232,7 @@
 		CLK_CKPER_HSE
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
-		CLK_ETH_DISABLED
+		CLK_ETH_PLL4P
 		CLK_SDMMC12_PLL4P
 		CLK_DSI_DSIPLL
 		CLK_STGEN_HSE
--- a/fdts/stm32mp15xx-dkx.dtsi
+++ b/fdts/stm32mp15xx-dkx.dtsi
@ -222,7 +222,7 @@
 		CLK_CKPER_HSE
 		CLK_FMC_ACLK
 		CLK_QSPI_ACLK
-		CLK_ETH_DISABLED
+		CLK_ETH_PLL4P
 		CLK_SDMMC12_PLL4P
 		CLK_DSI_DSIPLL
 		CLK_STGEN_HSE