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Pull out common code from aarch64 and include Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I4d0f5e1bb01bcdacbedf8e6c359de594239b645fpull/1932/head
Hadi Asyrafi
5 years ago
committed by
Sandrine Bailleux
Sandrine Bailleux
21 changed files with 21 additions and 266 deletions
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/* |
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch.h> |
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#include <asm_macros.S> |
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#include <cpu_macros.S> |
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#include <platform_def.h> |
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.globl plat_secondary_cold_boot_setup |
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.globl platform_is_primary_cpu |
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.globl plat_is_my_cpu_primary |
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.globl plat_my_core_pos |
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.globl plat_crash_console_init |
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.globl plat_crash_console_putc |
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.globl plat_crash_console_flush |
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.globl platform_mem_init |
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.globl plat_get_my_entrypoint |
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/* ----------------------------------------------------- |
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* void plat_secondary_cold_boot_setup (void); |
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* |
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* This function performs any platform specific actions |
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* needed for a secondary cpu after a cold reset e.g |
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* mark the cpu's presence, mechanism to place it in a |
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* holding pen etc. |
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* ----------------------------------------------------- |
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*/ |
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func plat_secondary_cold_boot_setup |
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/* Wait until the it gets reset signal from rstmgr gets populated */ |
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poll_mailbox: |
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wfi |
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mov_imm x0, PLAT_S10_SEC_ENTRY |
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ldr x1, [x0] |
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mov_imm x2, PLAT_CPUID_RELEASE |
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ldr x3, [x2] |
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mrs x4, mpidr_el1 |
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and x4, x4, #0xff |
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cmp x3, x4 |
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b.ne poll_mailbox |
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br x1 |
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endfunc plat_secondary_cold_boot_setup |
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func platform_is_primary_cpu |
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) |
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cmp x0, #PLAT_PRIMARY_CPU |
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cset x0, eq |
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ret |
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endfunc platform_is_primary_cpu |
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func plat_is_my_cpu_primary |
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mrs x0, mpidr_el1 |
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b platform_is_primary_cpu |
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endfunc plat_is_my_cpu_primary |
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func plat_my_core_pos |
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mrs x0, mpidr_el1 |
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and x1, x0, #MPIDR_CPU_MASK |
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and x0, x0, #MPIDR_CLUSTER_MASK |
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add x0, x1, x0, LSR #6 |
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ret |
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endfunc plat_my_core_pos |
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func plat_get_my_entrypoint |
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mov_imm x1, PLAT_S10_SEC_ENTRY |
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ldr x0, [x1] |
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ret |
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endfunc plat_get_my_entrypoint |
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/* --------------------------------------------- |
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* int plat_crash_console_init(void) |
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* Function to initialize the crash console |
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* without a C Runtime to print crash report. |
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* Clobber list : x0, x1, x2 |
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* --------------------------------------------- |
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*/ |
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func plat_crash_console_init |
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mov_imm x0, PLAT_UART0_BASE |
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mov_imm x1, PLAT_UART_CLOCK |
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mov_imm x2, PLAT_BAUDRATE |
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b console_16550_core_init |
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endfunc plat_crash_console_init |
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/* --------------------------------------------- |
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* int plat_crash_console_putc(void) |
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* Function to print a character on the crash |
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* console without a C Runtime. |
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* Clobber list : x1, x2 |
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* --------------------------------------------- |
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*/ |
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func plat_crash_console_putc |
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mov_imm x1, PLAT_UART0_BASE |
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b console_16550_core_putc |
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endfunc plat_crash_console_putc |
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func plat_crash_console_flush |
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mov_imm x0, CRASH_CONSOLE_BASE |
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b console_16550_core_flush |
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endfunc plat_crash_console_flush |
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/* -------------------------------------------------------- |
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* void platform_mem_init (void); |
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* |
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* Any memory init, relocation to be done before the |
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* platform boots. Called very early in the boot process. |
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* -------------------------------------------------------- |
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*/ |
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func platform_mem_init |
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mov x0, #0 |
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ret |
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endfunc platform_mem_init |
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.data |
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.align 3 |
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@ -1,57 +0,0 @@ |
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#include <arch_helpers.h> |
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#include <lib/xlat_tables/xlat_tables.h> |
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#include <lib/mmio.h> |
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#include <platform_def.h> |
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unsigned int plat_get_syscnt_freq2(void) |
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{ |
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return PLAT_SYS_COUNTER_FREQ_IN_TICKS; |
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} |
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unsigned long plat_get_ns_image_entrypoint(void) |
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{ |
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return PLAT_NS_IMAGE_OFFSET; |
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} |
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/******************************************************************************
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* Gets SPSR for BL32 entry |
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*****************************************************************************/ |
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uint32_t plat_get_spsr_for_bl32_entry(void) |
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{ |
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/*
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* The Secure Payload Dispatcher service is responsible for |
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* setting the SPSR prior to entry into the BL32 image. |
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*/ |
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return 0; |
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} |
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/******************************************************************************
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* Gets SPSR for BL33 entry |
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*****************************************************************************/ |
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uint32_t plat_get_spsr_for_bl33_entry(void) |
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{ |
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unsigned long el_status; |
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unsigned int mode; |
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uint32_t spsr; |
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/* Figure out what mode we enter the non-secure world in */ |
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; |
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el_status &= ID_AA64PFR0_ELX_MASK; |
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mode = (el_status) ? MODE_EL2 : MODE_EL1; |
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/*
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* TODO: Consider the possibility of specifying the SPSR in |
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* the FIP ToC and allowing the platform to have a say as |
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* well. |
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*/ |
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
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return spsr; |
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} |
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@ -1,22 +0,0 @@ |
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/* |
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* Copyright (c) 2019, Intel Corporation. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __PLAT_MACROS_S__ |
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#define __PLAT_MACROS_S__ |
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#include <platform_def.h> |
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/* --------------------------------------------- |
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* The below required platform porting macro |
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* prints out relevant platform registers |
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* whenever an unhandled exception is taken in |
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* BL31. |
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* --------------------------------------------- |
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*/ |
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.macro plat_crash_print_regs |
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.endm |
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#endif /* __PLAT_MACROS_S__ */ |
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@ -1,41 +0,0 @@ |
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved. |
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* |
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* SPDX-License-Identifier: BSD-3-Clause |
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*/ |
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#ifndef __PLATFORM_PRIVATE_H__ |
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#define __PLATFORM_PRIVATE_H__ |
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#include <common/bl_common.h> |
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/*******************************************************************************
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* Function and variable prototypes |
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******************************************************************************/ |
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void plat_configure_mmu_el3(unsigned long total_base, |
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unsigned long total_size, |
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unsigned long ro_start, |
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unsigned long ro_limit, |
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unsigned long coh_start, |
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unsigned long coh_limit); |
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void plat_configure_mmu_el1(unsigned long total_base, |
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unsigned long total_size, |
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unsigned long ro_start, |
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unsigned long ro_limit, |
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unsigned long coh_start, |
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unsigned long coh_limit); |
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void plat_gic_driver_init(void); |
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void plat_arm_gic_init(void); |
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void plat_delay_timer_init(void); |
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unsigned long plat_get_ns_image_entrypoint(void); |
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uint32_t plat_get_spsr_for_bl32_entry(void); |
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uint32_t plat_get_spsr_for_bl33_entry(void); |
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#endif /* __PLATFORM_PRIVATE_H__ */ |
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