From 447e699f70f1a1d1b85a8136b445eba689166c5d Mon Sep 17 00:00:00 2001 From: Boon Khai Ng Date: Fri, 6 Aug 2021 01:16:46 +0800 Subject: [PATCH] feat(intel): add macro to switch between different UART PORT HSD #1509626040: This patch is to add the flexibility for BL2 and BL31 to choose different UART output port at platform_def.h using parameter PLAT_INTEL_UART_BASE This patch also fixing the plat_helpers.S where the UART BASE is hardcoded to PLAT_UART0_BASE. It is then switched to CRASH_CONSOLE_BASE. Signed-off-by: Boon Khai Ng Change-Id: Iccfa7ec64e4955b531905778be4da803045d3c8f --- plat/intel/soc/agilex/bl2_plat_setup.c | 4 ++-- plat/intel/soc/agilex/bl31_plat_setup.c | 4 ++-- plat/intel/soc/common/aarch64/plat_helpers.S | 4 ++-- plat/intel/soc/common/include/platform_def.h | 1 + plat/intel/soc/n5x/bl31_plat_setup.c | 4 ++-- plat/intel/soc/stratix10/bl2_plat_setup.c | 4 ++-- plat/intel/soc/stratix10/bl31_plat_setup.c | 4 ++-- 7 files changed, 13 insertions(+), 12 deletions(-) diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c index 6e67502fb..03adcf318 100644 --- a/plat/intel/soc/agilex/bl2_plat_setup.c +++ b/plat/intel/soc/agilex/bl2_plat_setup.c @@ -71,8 +71,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, watchdog_init(get_wdt_clk()); - console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, - &console); + console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(), + PLAT_BAUDRATE, &console); socfpga_delay_timer_init(); init_ncore_ccu(); diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c index 168236b64..66d6b8f48 100644 --- a/plat/intel/soc/agilex/bl31_plat_setup.c +++ b/plat/intel/soc/agilex/bl31_plat_setup.c @@ -41,8 +41,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); - console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, - &console); + console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, + PLAT_BAUDRATE, &console); /* * Check params passed from BL31 should not be NULL, */ diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S index 5cb9b699a..213fd3cfe 100644 --- a/plat/intel/soc/common/aarch64/plat_helpers.S +++ b/plat/intel/soc/common/aarch64/plat_helpers.S @@ -102,7 +102,7 @@ endfunc plat_get_my_entrypoint * --------------------------------------------- */ func plat_crash_console_init - mov_imm x0, PLAT_UART0_BASE + mov_imm x0, CRASH_CONSOLE_BASE mov_imm x1, PLAT_UART_CLOCK mov_imm x2, PLAT_BAUDRATE b console_16550_core_init @@ -116,7 +116,7 @@ endfunc plat_crash_console_init * --------------------------------------------- */ func plat_crash_console_putc - mov_imm x1, PLAT_UART0_BASE + mov_imm x1, CRASH_CONSOLE_BASE b console_16550_core_putc endfunc plat_crash_console_putc diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index 785949391..d37904b79 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -168,6 +168,7 @@ #define PLAT_UART1_BASE (0xFFC02100) #define CRASH_CONSOLE_BASE PLAT_UART0_BASE +#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE #ifndef SIMICS_BUILD #define PLAT_BAUDRATE (115200) diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c index 2a8daa652..5ca1a716e 100644 --- a/plat/intel/soc/n5x/bl31_plat_setup.c +++ b/plat/intel/soc/n5x/bl31_plat_setup.c @@ -42,8 +42,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_64(PLAT_SEC_ENTRY, 0); - console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, - &console); + console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, + PLAT_BAUDRATE, &console); /* * Check params passed from BL31 should not be NULL, */ diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c index a8026ea0f..faff898d0 100644 --- a/plat/intel/soc/stratix10/bl2_plat_setup.c +++ b/plat/intel/soc/stratix10/bl2_plat_setup.c @@ -69,8 +69,8 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1, watchdog_init(get_wdt_clk()); - console_16550_register(PLAT_UART0_BASE, get_uart_clk(), PLAT_BAUDRATE, - &console); + console_16550_register(PLAT_INTEL_UART_BASE, get_uart_clk(), + PLAT_BAUDRATE, &console); socfpga_emac_init(); socfpga_delay_timer_init(); diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c index 128a8080d..f804c8ebf 100644 --- a/plat/intel/soc/stratix10/bl31_plat_setup.c +++ b/plat/intel/soc/stratix10/bl31_plat_setup.c @@ -49,8 +49,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY); - console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, - &console); + console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK, + PLAT_BAUDRATE, &console); /* * Check params passed from BL31 should not be NULL, */